i used to run vga monitor on my previous spartan 3 fpga kit on 4 mhz clock
now on my new kit the clock is of 10mhz
i wish to divide clock such that i get 4 mhz out of 10 mhz
how shall i do that in vhdl

If You can mutliply the clock with 2, the first divide by 5 and then multiply by 2. Could it be done ?

OK - I'm currently not firm in VHDL but can give you a concept:

1. Multiply the clock by 2 !
If no PLL is available: have one and the same counter incremented on the rising_edge
and on the falling_edge of the clock.
2. Divide the doubled frequency by 5.

This will result in a better duty cycle of the output than when first dividing and then
doubling - even if the input signal is not perfect.

Standard way of dividing a clock signal by a non-integer number is to dither the division ratio between the two nearest integers, so in this case a counter which divides by 2 half the time and three half the time, the instantaneous frequency is incorrect but on average it is.