![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)
Wishbone bus
by sidharth.sankar77 on Jun 21, 2013 |
sidharth.sankar77
Posts: 1 Joined: Jun 19, 2013 Last seen: Nov 5, 2014 |
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How wishbone bus is portable across all platforms like FPGA or ASIC ?
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RE: Wishbone bus
by moogyd on Aug 25, 2013 |
moogyd
Posts: 15 Joined: Nov 22, 2008 Last seen: Jun 26, 2019 |
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Yes
It is written in technology dependent RTL, so you can synthesize to any technology you like. Steven |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)