Hi @ all,

Has anyone of you gained some experience with Off-Chip Wishbone? As far as I know its the same as inside my SoC, but I wondered whether its feasible (and reasonable) to implement a Wishbone Interface using an external MCU. The reason why I came to this approach was to save ressources inside my FPGA.

Since I don't aim at high burst throughput (but at low latency), I have a lightweight implementation of Wishbone in mind.

Now please discuss, tell me if this is common - or a very bad idea.

Thanks in advance and kind regards,
Simon

Hi Simon,

I guess that you would need a MCU that already has a built-in wishbone master interface available on the pins. There might exists such MCUs, but I think your best option would be to create a bridge in your FPGA that can convert whatever interface the MCU is speaking to wishbone that you can use internally in your FPGA. I have been involved in projects that have done it that way.

If you just want to extend a wishbone interface between two FPGAs, there are some cores available at ohwr.org to serialize wishbone transactions that can be used to minimize the number of pins needed. But from your description, I guess that the first option is what you are looking for

Best Regards,
Olof Kindgren
olof@opencores.org

Hello Olof,

thanks for your support, from my current perspective (I've learned a lot the last days) I agree. I made some Top-Level changes to my design that makes this interface redundant. Nevertheless your post really helped me!

Regards,
Simon

Please consider this thread as

CLOSED :)