Hello,

I am using Xilinx 9.2 IDE and just working on Divide, Multiply and Mod Operators on a std_logic_vector signals. I dont find any problems on Multiply operator, come across the Error Xst 769 : "Operator must have constant operands or first operand must be power of 2" while synthesis.

Below is the simple piece of code i am working on

architecture Behavioral of div_op is
signal A_t, B_t, Q_t, M_t, R_t: integer range 0 to 1000;
begin
A_tB_tprocess(enable, A_t, B_t)
begin
if enable = '1' then
Q_tR_tM_tend if;
end process;
QMRend Behavioral;

Q, M and R are my 64 bits outputs.

When i synthesize, i get the aboive mentioned error. I cannot satisfy any of the conditions as mentioned in the error description.

Please Help,
Sincerely
Gaurav