Hello Folks!

When porting minsoc to the Digilent Atlys board (Spartan6) I got a strange error:
The Advanced Debug Bridge and gdb showed me there was some problem with the wishbone data.
I got the system running with another bitfile of mine which was build earlier for test. Only the newer ones have the problem - and I don't know the reason. Maybe I changed some code while snoop around in the code?!

(I'm sorry - the exact messages are not available, because I have not every day access to the board)

The adv. debug bridge says:
"ERROR! WB bus error during burst write, address 0x8FFFD (index ...), retrying!"


The gdb says to the start code:

ldi.hi r2,0x0000;
ldi.lo r2,0xcafe; (obviously a made-up content for this example...)
jr r2; (jump to addr pointed by r2)

that the content of GPR2 (with info spr) is:
0x8.CAFE


Both problems seem to me to have the same reason: The upper 2 byte of data have a stuck-at-1 behavior (0x0008.0000). After lines clearing the high part of a register (ldi.hi r2,0x00) the register still have 0x0008 .
The lower two bytes do also have a stuck at error - but I am not sure whether 0x0001 or 0x0008 (sorry for that :/ ).

My plan is to load a fresh minsoc source and repeat all my changes for the Atlys board. Nonetheless it would be very nice to know what was reason of this behaviour.

Thanks alot!

Cheers
Flo

ps. sorry for bad english - it's not my mother language

hey folks!

the error was fixed after some changes in the minsoc configuration and or1200 defines. see the minsoc: gdb set does not work -thread for details.

cheers!
flo