![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
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mutexnet
by sucheta on Jan 9, 2014 |
sucheta
Posts: 1 Joined: Sep 19, 2013 Last seen: Jan 2, 2017 |
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Hi,
I am doing my M-tech project on NoC router,and i wrote verilog code for mutexnet which is used in the arbiter of NoC router. for 2i/p mutex i am getting the output. but for 4 i/p mutexnet i am getting output as undefined state. I am using Xilinx software(Isim simulator) here is the circuit and code of mutexnet net. please let me know if any changes to be made in the code to get a correct output. please help me. regards sucheta
ss.doc.docx (44 kb)
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![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)