Please help me!!!
I have a project in my university for synchronous data transmition in VHDL. Project exercise is:

The system send 256 words with 8-bit in a paralel line. Transmition sinchroned in high CLK signal. The system read 256 words which transmitted from a synchron memory and start transmssion one cycle clk after START signal. All words transmitted in sequence from 0-255.
Words send in DATA bus, Id number send in NUM bus. The signal called ACTIVE shows if data are available in bus. After the last word(256) was transmitted, the system was waiting for START activation wich start a new trnsmition.

Project the system and make his implementation in VHDL

I done my project using verilog in synchronous as you said but for only 8 bit data transmission...is your data's transmission takes place b/w networks???