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All forums Other WISHBONE compatible PS/2 Controller - Connection to RISC32 CPU using partial addressing and test using Bus Functional Model
All forums Other WISHBONE compatible PS/2 Controller - Connection to RISC32 CPU using partial addressing and test using Bus Functional Model 
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WISHBONE compatible PS/2 Controller - Connection to RISC32 CPU using partial addressing and test using Bus Functional Model
by KwongCheong on Feb 10, 2014 |
KwongCheong
Posts: 2 Joined: Aug 12, 2012 Last seen: Oct 22, 2016 |
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Hi guys, I have a question about addressing for the WB compatible PS/2 controller. Supposed an address decoder is designed to output the necessary WB signals (STB_O, CYC_O, ADDR_O, WE_O, etc) to the WISHBONE interface of the PS/2 Controller, while it receives an acknowledge signal (ACK_I) from the WISHBONE interface to be noticed that the previous cycle is completed. Should I put the default signal for ACK_I into 1'b1 so that when I input a valid address into the address decoder, it can output the WB compatible output signals to the WISHBONE interface? What should the signal for acknowledge signal (ACK_O) for the WISHBONE interface be when it is idle?
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RE: WISHBONE compatible PS/2 Controller - Connection to RISC32 CPU using partial addressing and test using Bus Functional Model
by KwongCheong on Feb 11, 2014 |
KwongCheong
Posts: 2 Joined: Aug 12, 2012 Last seen: Oct 22, 2016 |
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Hi guys, I have a question about addressing for the WB compatible PS/2 controller. Supposed an address decoder is designed to output the necessary WB signals (STB_O, CYC_O, ADDR_O, WE_O, etc) to the WISHBONE interface of the PS/2 Controller, while it receives an acknowledge signal (ACK_I) from the WISHBONE interface to be noticed that the previous cycle is completed. Should I put the default signal for ACK_I into 1'b1 so that when I input a valid address into the address decoder, it can output the WB compatible output signals to the WISHBONE interface? What should the signal for acknowledge signal (ACK_O) for the WISHBONE interface be when it is idle?
b_addr_decoder.v (2 kb)
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