I thought that this could of great interest to you guys designing open-source hardware here on OpenCores.

We (Synflow) are creating a new programming language that makes it much faster (and easier too) to design hardware. This language can be transformed to VHDL or Verilog code that is synthesizable, platform-agnostic, and readable. We've recently open sourced the compiler, IDE, and VHDL code generator.

If you're interested or if you have any questions, come and join us on our forum at https://forum.synflow.com

Cheers!
Matthieu

Any comparison with, e.g., SystemVerilog?

We haven't made any comparison with SystemVerilog, but they are fundamentally different at the core. Our language is structured, so you have conditionals, loops, function calls that can be used in both combinational style (as in Verilog/VHDL/SystemVerilog) and synchronous style (as in none of these languages!). So instead of writing (Verilog/VHDL/SystemVerilog style):

if (rising edge) {
  switch (state) {
  case s0:
    i = 0;
    state <= s1;
  case s1:
    if (i <= 10) {
      i <= i + 1;
      dout = i;
      state <= s1;
    } else {
      state <= s2;
    }
  case s2:
    print("done");
  }
}

You would just write this in our language:

for (i = 0; i <= 10; i++) {
  dout.write(i);
}
print("done");

Which, I think you'll agree, is pretty awesome :-)