Hi All

I am a system engineer currently working on Avionics application, where in Actel ProASIC 3E3000L -1 MIL grade FPGA is being used to build system level requirements.

Currently I am finished with my design and design needs to be given to third party company for IV&V. So I want secure my source code by creating custom IP that can be synthesizable and can verified.

Kindly assist me on how to create a custom IP core in Libero or any other software. Does Libero have Core generator option like Xilinx.


Thanks in advance, I will be waiting for your valuable inputs.