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Wishbone interface by justintime on Feb 10, 2015			justintime Posts: 1 Joined: Dec 6, 2014 Last seen: Feb 16, 2018
I'm a bit (actually, a lot) confused by the description from WB4 specs: Classic standard SINGLE WRITE Cycle CLOCK EDGE 1 SLAVE asserts [ACK_I] in response to [STB_O] to indicate latched data. CLOCK EDGE 2 SLAVE latches data on [DAT_O()] and [TGD_O()]. So, when exactly does Slave latche data - at Clock Edge 1, edge of ACK_I or Clock Edge 2 ??? Basically, when does Master can safely remove all signals during single write cycle ? I'm a bit (actually, a lot) confused by the description from WB4 specs: Classic standard SINGLE WRITE Cycle CLOCK EDGE 1 SLAVE asserts [ACK_I] in response to [STB_O] to indicate latched data. CLOCK EDGE 2 SLAVE latches data on [DAT_O()] and [TGD_O()]. So, when exactly does Slave latche data - at Clock Edge 1, edge of ACK_I or Clock Edge 2 ??? Basically, when does Master can safely remove all signals during single write cycle ?

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