Good afternoon everyone,



I'm currently writting a component in order to watch what is going with a memory controller:

I'm working in the memory controller of the leon3 available on gaisler/aeroflex website.

Long story, short:

I want to make a component which I can use to monitor a range of adress (I have check the component alone, not with simulation of the whole projet, and not in the actual project).

I already declare the new ahb_menbar in the hconfig of the mctrl but I can't reach (in grmon on the real design, so on the card) the component (as manual said):

So I check the address which contains configuration for slaves/masters.

I found all previous corresponding configuration (aka IO/RAM/ROM, as manual said and so the vhdl is coherent with it).



I can't still see what I have done (ie adding a new one on the actual design).

For information:

I use xilinx ISE, and the component is not trimed (on the rtl), the test signal are also connected, but not used in the component.


So here's my QUESTIONS:
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Is(/are) there any another thing(s) other than hconfig to set an address to a component ?

Do I need to add Scan Support (as mentionned in the grlib page 57) ?

Or is it only for the sake of info sys (in grmon) or the simulation ?
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Notes:

I tried to use ChipScope Pro but it just s***w my projet and had to start from another backup projet but from now on, I don't that's going to help me anyway.

I wish I already contribute to opencores but the really only useful stuff I made is a configurable CRC and someone already did it.

I guess I just made only some sutdent level stuff not engineer (serial communication, DSP).


Thanks you,

Sorry for the english