Hello all.
I have a question about Verilog. I'm not an Verilog expert, so a kind of Verilog code looks strange for me. Let me demonstrate an example (I often found such coding style):

Attention! In the following examples I use "=" instead of normal "non-blocking assignment" just to overcome conflict with HTML syntax.

reg rfoo;
always @(posedge clk) begin
rfoo = 0;
if( /* a condition */)
rfoo = 1;
end

It looks that behavior is equivalent to:

reg rfoo;
always @(posedge clk) begin
if( /* a condition */)
rfoo = 1;
else
rfoo = 0;
end

Am I right?
Is the style compliance with Verilog rules or is it "unofficial" but popular extension?

I am certainly no expert in Verilog, but my first impression is that the first example, while it may simulate "correctly," is not synthesizeable, as you are effectively assigning rfoo to potentially two different states each clock cycle.

The second, while more... shall we say "verbose," should be synthesizable and not cause a glitch in simulation

Actually, I've got clarification from Stefan Kristiansson on. Let me cite his answer: "assignments like that within an always block works from top-to-down, i.e. the owns closer to bottom overrides the ones closer to the top."
The construction is legal both for simulation and synthesis.

As per my knowledge in verilog. The first block will infer a sequential logic (ff or latch) whereas the second block will infer a combinational logic (gate or mux). Because for the first block when there is false condition the reg rfoo will maintain its previous value rather that opposite value of the true condition.