I am interested in FPGA utilization reports of soft cores and I came across this list from James Brakefield:

Small soft core uP Inventory

https://www.google.com/url?q=http://opencores.org/usercontent,doc,1393289940&sa=U&ved=0CAoQFjACahUKEwjaxJyP7e7GAhUhAHMKHUY_Dlo&client=internal-uds-cse&usg=AFQjCNGZk5AVlOrMboKuYyTn1dywhr3R7g

It is a very comprehensive list. But I have some question about it.
In particular for the ARM_Cortex_A9, the list reports a 4500 LUTS/ALM count, but how was that number obtained? Is that a soft implementation or an estimation from an ASIC? Was it implemented on xilinx or altera FPGA?

Best Regards,
Raul.

Have you checked out the rest of the files on the project page? You'll find a summary there, and a link to "Download" other files (mostly documents in this case) at the top of the page.

Dan

Hello Dan,

I have read about the project and i have checked a more detailed spreadsheet from the project page. According to the notes under the "reference" column, the 4500 lut usage count for an ARM Cortex A9 is estimated using xilinx tools:

xilinx plan ahead: an A9 core is 7.6% of device

So is it correct to assume that a way to estimate the area of a hardened cortex a-9 in terms of luts is to use floorplaning tools? Is this a common approach? Do you know any other project that uses this methodology to obtain lut usage of a hardened arm processor?

When I read through his spreadsheets, I got the sense that he used whatever tools he had available, and to some extent struggled to collect all the data given that he received LUT counts from multiple methods and sources.

Perhaps I should turn your question around, as I'd be curious to hear your answer: How would you recommend measuring the space usage of a processor core?

Dan

I have actually used a similar approach:

I use Xilinx's floorplaning tools to count the logic blocks around the hardened Arm core in a Zynq chip.

Zynq Chip
_____________________
l l |
l ARM l |
l Core l y |
l___________l |
l x |
l FPGA |
l |
l_____________________|

From the floor planning tool I count x "luts in length" and y "luts in height" and I come up with 6400 luts. Wich is different -but not that far- from the 4500 luts calculated by James Brakefield. I think that the lut count can be different depending on the exact device used.

However, I would like to know if this a valid methodology and if this way of counting/estimating reconfigurable area for a hardened core has been used before or reported somewhere else?

Raul.

Hi,

You asked, "In particular for the ARM_Cortex_A9, the list reports a 4500 LUTS/ALM count, but how was that number obtained? Is that a soft implementation or an estimation from an ASIC?"

The ARM Cortex-A9 as found in the Xilinx Zynq and the Altera SoC-fpga is not a "soft core" and it is not implemented in "LUTs."

The Altera and Xilinx ARM Cortex-A9 processor blocks are "gate level" designs, implemented using "transistors," not "LUTs." The usual way of describing ASIC resource consumption would be in "gate count" or "transistor count" for a particular implementation, or in square millimeters (mm2) for some process & node.

According to Wikkipedia (https://en.wikipedia.org/wiki/Transistor_count) an A9 implementation takes about 26 million transistors. You can translate that to equivalent gate count using your favorite conversion formula.

The size of the A9 core will depend on the synthesis tools used and the constraints applied. You can take the same a9 and implement it for the fastest speed, or you can implement it for the lowest power. According to ARM (Osprey_Analyst_Presentation_v2a.pdf) the speed optimized A9 is 6.7 mm2 in TSMC 40nm, while the power optimized version of the same core is 4.9mm2 in the same process/node.

Now that you know from above that a Cortex-A9 takes 6.7mm2 in a 40nm process, you can apply your shrink factor correction to get a ballpark figure for size of the core in the 28nm process node.

Now, back to the "Small soft core uP Inventory," I think that one way of explaining what the author was trying to get at was "How many luts did the fpga fabric have to give up so that the A9 would fit on the die?" That is to say, if you have a fixed die size goal for the entire chip, you have to give up some luts to make the processor block bigger, or you would have to make the processor block smaller if you wanted to fit a larger fpga fabric on the same die size. In that case it makes sense to say that the Cortex-A9 block consumed the same area that could have been used to implement 4500 luts.

This begs the question, what if you had the verilog or vhdl source code for the Cortex-A9, what size fpga would you need to implement it? I'm guessing it will be more than 4500 LUTs.

I hope that helps,
Good Luck,
Richard.

Hello Richard,

Thank you for your comments. You are correct:

"This begs the question, what if you had the verilog or vhdl source code for the Cortex-A9, what size fpga would you need to implement it? I'm guessing it will be more than 4500 LUTs."

A design implememted in FPGAs definitely would require more resources than 4500 LUTs. Let me rephrase my original question: if the hardened ARM Cortex-A9 in a zynq chip were removed, how many luts could fit in that same area?. Using xilinx floorplaning tools I calculated 6400 luts by multiplying the number of luts in x by the number of luts in y around the Cortex A-9. Do you think that this can be considered a correct approach?

Raul.

Raul,

That sounds like a valid approach to answer the question you just asked, "if the hardened ARM Cortex-A9 in a zynq chip were removed, how many luts could fit in that same area?"

My question for you is, what relevance or significance would the answer to this question have? Removing the ARM would necessitate a hardware redesign. Why not just pick an existing chip with the area you need in LUTs already?

Dan