I've been somewhat diverted learning amazon web services (AWS and achieving all certs!) so looking forward to catching up on recent events. There's a new virtual box, new vagrant (1.8), new GHDL 0.33, risc-v seems zync (yes I'm a little behind the curve) and Intel bought Altera (finalized 28 Dec, 16.7 billion)!

Anyway with the new year, back to basics; one key reason I like the fpga model is the inherent parallelism. Rather than a single program counter register determinining the next action, sets of pins or sets of transistors can be completely different state machines [of arbitrary complexity]. I feel that fpga provides a much better neural model than the microprocessor/ALU.

In cloud infrastructure there's a related movement towards 'microservices'. With this idea you might split up your web services into a few or a few thousand micro-service elements running on a few hundred virtual servers. There is a dissatisfaction with single monolithic programs mixing all the functions into one [scaled] service. In terms of mentalism I thing there's also a link to better neural modelling; and the fact that the model typically isn't well supported in virtual hardware reinforces that it's a conceptual goal!

The challenges in fpga have their neural analogs. There are real heat/energy budgets; for example I like that Embecosm's association with Bristol Uni includes 'investigating novel ways to reduce energy consumption of embedded systems'. It would be great to have more dynamic means for managing energy in running fpga maps, which I would relate back to the plight of persons who might tend to feint or fit under stress.

I was sad to read around the OpenRISC - ASIC Funding that there are questions about where the donations went. On the other hand maybe the goal wasn't big and hairy and audacious enough. Since both of Xilinx and Altera were fabless, surely the open community could practically embrace an open design for an actual fpga.

An open fpga might only have a small number of LUTs etc, but could initate more innovative models such as establishing areas of the chip that can be reloaded with a replacement image, under program control. I would relate the importance of this step to the introduction of Job Control Languages (JCL) which was a huge innovation back in the punched card era. Further, we could learn from more recent innovations in linux libvirt and cgroups to make direct but regulated access to shared resources such as pins a part of the hosted operating system on the open fpga.

Happy New Year to All - may all your resolutions stick!

Best regards,
StephenH

And a Happy New Year to you as well, Steve.

I would be curious, and even excited to see someone figure out how to handle
allocating FPGA resources across multiple users and/or processes connected to
a host server. Even more than that, I would be fascinated to see if FPGA's
could handle context swaps.

Perhaps FPGA resources could be turned into blocks or cores that would occupy
an address space on a (wishbone or other) bus? Then, as long as the context or
state of the core could be preserved, the capability could be added or removed
from the bus at will.

A fascinating thought to start a new year,

Dan

On the topic of open source FPGA, check this out: https://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html