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Simple bus to AXI4
by omikron88 on Jun 3, 2016 |
omikron88
Posts: 1 Joined: Nov 2, 2008 Last seen: May 11, 2023 |
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I have simple desingn in Zynq, using Z80 like bus:
D(7:0) A(n:0) MREQn RDn WRn CLK and I need connect it to use Zynq's DDR3 controller as SRAM for it. Any idea or open core how to do that? |
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RE: Simple bus to AXI4
by dgisselq on Jun 4, 2016 |
dgisselq
Posts: 247 Joined: Feb 20, 2015 Last seen: Oct 24, 2024 |
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There are a variety of OpenCores projects that you might find useful in your quest. Here's an AXI4-Lite to wishbone bridge, just what you are trying to do, only it bridges to the Wishbone or IPB bus instead of your special bus. You might also find the AXI4 bus functional model useful.
Dan |
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