Hi,

Maybe someone will have idea how to solve my problem with always block simulated in Icarus Verilog. In the code below I would like to perform or operation of array.

wire [`WIDTH-1:0] periph_upstream_data [CFG_CONF_NUM-1:0];

always @(*) begin
upstream_data = {`WIDTH{1'b0}};
for (i = 0; i upstream_data = upstream_data | periph_upstream_data;
end
end

The above code works well in every commercial tool from ASIC (successfull tapeouts) to FPGA (working boards), verilator etc. Only Icarus Verilog has a problem. It hangs in this block forever from the start.

When I modify code to like this:

always @(*) begin
#1;
upstream_data = {`WIDTH{1'b0}};
for (i = 0; i upstream_data = upstream_data | periph_upstream_data;
end
end

simulation runs ok, so I'm sure this is the cause. The problem is that array is configurable and I cannot put the whole array in the sensitivity list so it looks like it is sensitive to upstream_data and loops forever.

Any ideas? Maybe how to write it in different way?

Did you copy and paste that code properly? I'm not seeing the three items within the for loops definition, and ... it really looks to me like a huge syntax error. Are you sure this even works?

Dan

It is definitely not what I was sending. Forum engine is altering my message...