OpenCores
no use no use 1/2 Next Last
Performance Evaluation for SoC Platforms
by leeweide on Jun 20, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
Hello everyone (:

I have a question with regards to the evaluating of the performance of SoC platforms in SoC chips.

I am currently working on an SoC chip in which I have to conduct performance test to evaluate the platform's performance in terms of throughput and latency.

As I am inexperienced in this field, may I ask if anyone can point me to resources such as books, or white papers or academic papers from companies like Synopsys or Cadence that is related to performance evaluation of SoC platforms?

I have tried searching on Google but so far I have read papers that use proprietary software, e.g. Mirabilis VisualSim, however, I need to build one from scratch using either Verilog (preferably) or SystemC. Are there any papers that present performance evaluation of SoC platforms without linking to the use of proprietary software?

Thank you very much for all of your kind help~ :):)
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 20, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
May I advice you to look at P.Chu's book "RTL Hardware Design" table 6.2
You can create (build) a such table for your chip. Setup PLL = 300 MHz and you'll see all the performance
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 24, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
May I advice you to look at P.Chu's book "RTL Hardware Design" table 6.2
You can create (build) a such table for your chip. Setup PLL = 300 MHz and you'll see all the performance


Thank you js_cpp for your kind help! :) I will take a look at it (: Just wondering, may I ask if there are equivalent books in Verilog? :x

Thank you once again for your help! :)
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 24, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
May I advice you to look at P.Chu's book "RTL Hardware Design" table 6.2
You can create (build) a such table for your chip. Setup PLL = 300 MHz and you'll see all the performance


Hi js_cpp. May I ask if you meant Table 6.2 on Page 132 of the book? May I ask if you can elaborate more on this? This is because I am unable to see the link between the table and setting PLL = 300MHz to generate the table.

Just to be sure that I am looking at the correct table, the table is labeled, "Circuit area and delay of some commonly used VHDL operators". Am I right?

I am sorry for being so lost as I am new to this and I would love to get more advice from you and also from the Community.

Thank you once again! (:
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 24, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
One day I develop CAN-interface controller
In short there is a data block up to 64 bytes or 512 bits. To read/write all the bits at the baud rate 2MB I increment counter. When I work with sysClk=50MHz all work fine. I set PLL=200 MHz and voila! Slacks!
Do you understand me?
There are two common summators CSA and CRA. When you implement ++i what incrementor you'll get?
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 24, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
Here no Verilog, but C++ :))
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 24, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
One day I develop CAN-interface controller
In short there is a data block up to 64 bytes or 512 bits. To read/write all the bits at the baud rate 2MB I increment counter. When I work with sysClk=50MHz all work fine. I set PLL=200 MHz and voila! Slacks!
Do you understand me?
There are two common summators CSA and CRA. When you implement ++i what incrementor you'll get?


I see. (: I am not sure if I had understand you correctly, but do you mean that you calculate the time it takes for a data block of size 512 bits to be read/write (independently) over a 2MB baud rate communication system?

Why do you say that when clock=50MHz it works fine but at 200MHz, it becomes slack?

May I ask what are CSA and CRA? ++i means pre-increment but what do you mean by the 'incrementor'?
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 24, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
Here no Verilog, but C++ :))


Ah I see (: No worries. I'm not good at C++ but I know some C fundamentals. Haha (:
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 24, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
No, you understand me incorrectly.
I use the state machine. When machine says "time to collect data" I must count bits
Now I have one of two ways: (1) count up to desired nBits or (2) preset the counter to nBits and count backward to 0 (?: what method is prefer or better? :)).
It was my task
Your task is to check (validate) table 6.2
How to do that?
There are two ways, too: the theoretical (open the chip's datasheet, write to a sheet all desired properties and sum them all. Uffffff) and the practical (You describe a workable schema and compile the project, then the fpga-compiller show you all hot points)
When you change compilator-chip-vendor you'll recompile the exists project and compilator points to the hot points again

RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 25, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
No, you understand me incorrectly.
I use the state machine. When machine says "time to collect data" I must count bits
Now I have one of two ways: (1) count up to desired nBits or (2) preset the counter to nBits and count backward to 0 (?: what method is prefer or better? :)).
It was my task
Your task is to check (validate) table 6.2
How to do that?
There are two ways, too: the theoretical (open the chip's datasheet, write to a sheet all desired properties and sum them all. Uffffff) and the practical (You describe a workable schema and compile the project, then the fpga-compiller show you all hot points)
When you change compilator-chip-vendor you'll recompile the exists project and compilator points to the hot points again



Thank you js_cpp for the clarifications. I am sorry for misunderstanding the points you have made.
I think counting up to the desired nBits is better because if I were to count back to 0, I may have to deal with the reset case. Am I right?

I think I am not familiar with FPGA compilers hence I am not clear about the concept of hot-points. Do you mean bottlenecks in the system? :)

Thank you for your guidance and for the detailed explanation.
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 25, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
Do you know what is the slack?
when compiler found one of them it color it to red. so, hot-point ;)
Perhaps it is not general practice to call them 'hot-point'...
About count up
What is comparator? Which comparator is simpler a common (a==b) or a simple (0==a)?
The cost of operation '++' is the same to '--'. So, …
All about these I read from P.Chu's book. And it is independent to the language
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 25, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
There are tons of beautiful books on Verilog and about Verilog. But you must find them yourself.
RE: Performance Evaluation for SoC Platforms
by js_cpp on Jun 25, 2019
js_cpp
Posts: 11
Joined: Nov 2, 2014
Last seen: Nov 14, 2019
May I advice you to start from P.Chu's site?
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 26, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
Do you know what is the slack?
when compiler found one of them it color it to red. so, hot-point ;)
Perhaps it is not general practice to call them 'hot-point'...
About count up
What is comparator? Which comparator is simpler a common (a==b) or a simple (0==a)?
The cost of operation '++' is the same to '--'. So, …
All about these I read from P.Chu's book. And it is independent to the language


On slack:

Ah this is new to me. Oh dear. I have a lot to learn about digital systems :( Sorry for being so lacking in knowledge. I Googled and found this: http://asic-soc.blogspot.com/2013/08/setup-and-hold-slack.html
May I ask if you were referring to the above as 'slack'? :)

On comparator:

A comparator compares 2 inputs and outputs the results correspondingly. For example, comparing 2 1-bit inputs, if A = 0, B = 1, then (A = B) ==> 0, (A 1, (A > B) ==> 0.
I think the simple (0==a) comparator will be easier. This is because for the 0, I can tie it to ground. Am I right?

On ++:

Ah yes, I would think so, from hardware perspective, because ++ is like incrementing a variable, like count = count + 1.

On P.Chu's book:

I saw that he has written a lot of books :) I will check them out :) Thank you :)
RE: Performance Evaluation for SoC Platforms
by leeweide on Jun 26, 2019
leeweide
Posts: 8
Joined: Feb 28, 2019
Last seen: Jan 9, 2020
May I advice you to start from P.Chu's site?


Yes, thank you js_cpp for your advice.

I am sorry for the bolded text in my previous reply and I have not meant the words to be bolded.
no use no use 1/2 Next Last
© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.