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SoC with pipelined RISC-V CPU using pure nMigen language - no VHDL/Verilog
by lekernel on Jun 24, 2019 |
lekernel
Posts: 11 Joined: Feb 3, 2008 Last seen: Aug 14, 2019 |
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Hi,
I wanted to share some cool results from a project we've been working on. Here is a proof-of-concept mini-SoC with a pipelined RISC-V core running at 100MHz in a Lattice ECP5 FPGA, with everything written in a new Python-based HDL called nMigen (https://github.com/m-labs/nmigen/). It can run simple programs written in the Rust programming language (C and other languages should work as well, but are less interesting). https://git.m-labs.hk/m-labs/heavyx The compilation is done entirely with the open source FPGA toolchain, and it is relatively fast. There is no Verilog or VHDL involved at all, nMigen generates intermediate representation (IR) for the Yosys synthesizer directly. You can even compile bitstreams on Android phones easily by installing Nix on them (not that it's very useful, but it's fun and shows we've gone a long way since proprietary toolchains). Sébastien |
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