Hello Adalbert, I have successfully ported the code to an Altera Cyclone. The blocks you need to change to go from Xilinx to Altera are the tprams (dual-port rams) used in the FIFOs and any internal block rams. I also added a PLL instance to keep the internal clock locked to the input pciclock. You can use the megafunction generator to generate the dual-port rams and PLL. Good luck. Regards, Manoj ============================= Manoj Viswambharan Consulting Hardware Engineer manojv@optonline.net ============================= --- adalbert.mueller@web.de wrote: http://www.opencores.org/mailinglists.shtml __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading and sharing. http://photos.yahoo.com/

Hi Manoj,

I even changed the tpram files and had success in compiling the core
together with HPI. But till no, I don't know if it's working. I'm just
configuring the BAR's and next step will be to try to communicate.

Bye,

Adalbert



mv wrote:

Hello Adalbert, Does the post-place-and-route simulation pass? If it doesn't, than bench testing won't help. As you know it's easier to debug in the simulator. Get this to pass first before going to the bench. Also perform timing simulation after this step. It will be S-L-O-W but run it as long as you can. It does help shake out some hard to find bugs. The best way to debug the FPGA on the bench (IMHO) is the SignalTap logic analyzer megacore (or Xilinx Chipscope for Xilinx FPGAs). If you have room in the FPGA, you can instantiate this core along with the rest of your logic. The QuartusII GUI has a decent way of capturing and displaying the events on screen. The GUI uses the JTAG interface to communicate with the FPGA. There are are lots of articles and Appnotes on Altera's website Re: SignalTap. Aside: I'm not an advocate of any FPGA vendor, I just happened to use Altera for this project. I've used Xilinx, Actel, & Lattice on other projects. Any of which will do the job. I used the logic analyzer core to view the Wishbone bus. It's a very useful tool for debugging internal FPGA signals. When prototyping with the FPGA make sure to pick a larger FPGA than required for the logic. The SignalTap core uses a lot of block rams depending on your capture depth. Instantiate the core and check the resource utilization before committing to the board design. If you don't have room for the logic analyzer core, then try buffering and bringing out the signals of interest to unused pins on the FPGA. You can hook up an external logic analyzer to these pins to view the signals. It helps if you had some spare pins going to a test connector. SignalTap has a mode that can do this for you. I also used a PCI Analyzer/Exerciser to view the PCI bus signals and generate bus cycles. You can rent one for about a $1500/month if needed. Good Luck. Regards, Manoj ======================================= Manoj Viswambharan Consulting Hardware Engineer manojv@NOSPAMoptonline.net Remove NOSPAM for actual email address. ======================================= --- "adalbert.mueller" adalbert.mueller@web.de> wrote: __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading and sharing. http://photos.yahoo.com/

Hi again Manoj,

at the moment I have some trouble in getting the core to run. I seems to
be an timing issue. Sometimes he isn't recognized, sometimes he is
recognized but not configured (because the BAR's are not writeable),
sometimes some bits are wrong.
What tool do you use and have you set some constraints?
I'm using quartus web edition. I've played around with the
setup/hold/clock2output times but had no success.

Suggestions are welcome ;-)

Best regards,

Adalbert Mueller

adalbert.mueller wrote:

can I use it with EP2C8Q208 ?
any experiences ?thanks