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hierarchy of the design
by Unknown on Jan 19, 2004 |
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We cant seem to be able to finf the module definition for
RAMB4_S16_S16 as well as RAM16X1D. Kindly assist.
Thanks.
--Nisha
----- Original Message -----
From: "PinhasNBeatris Krengel" bknpk@h... >
To: pci@o...
Date: Sat, 01 Jun 2002 13:56:49 +0000
Subject: [pci] hierarchy of the design
I wrote a little perl script that extracts the design hierarchy. I
think it is handy to have it. Attached is the report for this design. Any remarks are wellcomed. module: PCI_PARITY_CHECK mod: PAR_CRIT ref: par_gen mod: PERR_CRIT ref: perr_crit_gen mod: PERR_EN_CRIT ref: perr_en_crit_gen mod: SERR_CRIT ref: serr_crit_gen mod: SERR_EN_CRIT ref: serr_en_crit_gen module: PCI_TARGET_UNIT mod: DELAYED_SYNC ref: del_sync mod: PCIW_PCIR_FIFOS ref: fifos mod: PCI_TARGET32_INTERFACE ref: pci_target_if mod: PCI_TARGET32_SM ref: pci_target_sm mod: WB_MASTER ref: wishbone_master module: WB_ADDR_MUX module: CBE_EN_CRIT module: OUT_REG module: PCI_TPRAM mod: RAM16X1D ref: ram00 mod: RAM16X1D ref: ram01 mod: RAM16X1D ref: ram02 mod: RAM16X1D ref: ram03 mod: RAM16X1D ref: ram04 mod: RAM16X1D ref: ram05 mod: RAM16X1D ref: ram06 mod: RAM16X1D ref: ram07 mod: RAM16X1D ref: ram08 mod: RAM16X1D ref: ram09 mod: RAM16X1D ref: ram10 mod: RAM16X1D ref: ram11 mod: RAM16X1D ref: ram12 mod: RAM16X1D ref: ram13 mod: RAM16X1D ref: ram14 mod: RAM16X1D ref: ram15 mod: RAM16X1D ref: ram16 mod: RAM16X1D ref: ram17 mod: RAM16X1D ref: ram18 mod: RAM16X1D ref: ram19 mod: RAM16X1D ref: ram20 mod: RAM16X1D ref: ram21 mod: RAM16X1D ref: ram22 mod: RAM16X1D ref: ram23 mod: RAM16X1D ref: ram24 mod: RAM16X1D ref: ram25 mod: RAM16X1D ref: ram26 mod: RAM16X1D ref: ram27 mod: RAM16X1D ref: ram28 mod: RAM16X1D ref: ram29 mod: RAM16X1D ref: ram30 mod: RAM16X1D ref: ram31 mod: RAM16X1D ref: ram32 mod: RAM16X1D ref: ram33 mod: RAM16X1D ref: ram34 mod: RAM16X1D ref: ram35 mod: RAM16X1D ref: ram36 mod: RAM16X1D ref: ram37 mod: RAM16X1D ref: ram38 mod: RAM16X1D ref: ram39 mod: RAMB4_S16_S16 ref: ramb4_s16_s16_1 mod: RAMB4_S16_S16 ref: ramb4_s16_s16_2 module: CONF_CYC_ADDR_DEC module: FRAME_CRIT module: PCI_TARGET32_CLK_EN module: WB_SLAVE mod: async_reset_flop ref: async_reset_as_wbr_flush mod: synchronizer_flop ref: command_bit_sync mod: synchronizer_flop ref: isr_bit0_sync mod: synchronizer_flop ref: isr_bit1_sync mod: synchronizer_flop ref: isr_bit2_sync mod: synchronizer_flop ref: pci_err_cs_bits_sync mod: SYNC_MODULE ref: sync_isr_1 mod: SYNC_MODULE ref: sync_isr_2 mod: SYNC_MODULE ref: sync_isr_3 mod: SYNC_MODULE ref: sync_isr_4 mod: SYNC_MODULE ref: sync_pci_err_cs_8 mod: SYNC_MODULE ref: sync_status_11 mod: SYNC_MODULE ref: sync_status_12 mod: SYNC_MODULE ref: sync_status_13 mod: SYNC_MODULE ref: sync_status_14 mod: SYNC_MODULE ref: sync_status_15 mod: SYNC_MODULE ref: sync_status_8 mod: SYNC_MODULE ref: sync_wb_err_cs_8 mod: synchronizer_flop ref: wb_err_cs_bits_sync module: PAR_CRIT module: PCIW_PCIR_FIFOS module: WB_SLAVE_UNIT mod: CONF_CYC_ADDR_DEC ref: ccyc_addr_dec mod: DELAYED_SYNC ref: del_sync mod: DELAYED_WRITE_REG ref: delayed_write_data mod: WBW_WBR_FIFOS ref: fifos mod: PCI_MASTER32_SM_IF ref: pci_initiator_if mod: PCI_MASTER32_SM ref: pci_initiator_sm mod: WB_ADDR_MUX ref: wb_addr_dec mod: WB_SLAVE ref: wishbone_slave module: FRAME_LOAD_CRIT module: PCI_BRIDGE32 mod: CONF_SPACE ref: configuration mod: PCI_IN_REG ref: input_register mod: CUR_OUT_REG ref: output_backup mod: PCI_PARITY_CHECK ref: parity_checker mod: PCI_IO_MUX ref: pci_io_mux mod: PCI_RST_INT ref: pci_resets_and_interrupts mod: PCI_TARGET_UNIT ref: pci_target_unit mod: WB_SLAVE_UNIT ref: wishbone_slave_unit module: PCI_TARGET32_DEVS_CRIT module: PERR_CRIT module: CUR_OUT_REG module: PCI_DECODER module: PCI_TARGET32_INTERFACE mod: async_reset_flop ref: async_reset_as_pcir_flush module: PERR_EN_CRIT module: DECODER module: PCI_IN_REG module: SERR_CRIT module: WBW_WBR_FIFOS module: DELAYED_SYNC mod: synchronizer_flop ref: comp_sync mod: synchronizer_flop ref: done_sync mod: synchronizer_flop ref: req_sync mod: synchronizer_flop ref: rty_exp_back_prop_sync mod: synchronizer_flop ref: rty_exp_sync module: IRDY_OUT_CRIT module: PCI_IO_MUX mod: PCI_IO_MUX_AD_EN_CRIT ref: ad_en_high_gen mod: PCI_IO_MUX_AD_EN_CRIT ref: ad_en_low_gen mod: PCI_IO_MUX_AD_EN_CRIT ref: ad_en_mhigh_gen mod: PCI_IO_MUX_AD_EN_CRIT ref: ad_en_mlow_gen mod: OUT_REG ref: ad_iob0 mod: OUT_REG ref: ad_iob1 mod: OUT_REG ref: ad_iob10 mod: OUT_REG ref: ad_iob11 mod: OUT_REG ref: ad_iob12 mod: OUT_REG ref: ad_iob13 mod: OUT_REG ref: ad_iob14 mod: OUT_REG ref: ad_iob15 mod: OUT_REG ref: ad_iob16 mod: OUT_REG ref: ad_iob17 mod: OUT_REG ref: ad_iob18 mod: OUT_REG ref: ad_iob19 mod: OUT_REG ref: ad_iob2 mod: OUT_REG ref: ad_iob20 mod: OUT_REG ref: ad_iob21 mod: OUT_REG ref: ad_iob22 mod: OUT_REG ref: ad_iob23 mod: OUT_REG ref: ad_iob24 mod: OUT_REG ref: ad_iob25 mod: OUT_REG ref: ad_iob26 mod: OUT_REG ref: ad_iob27 mod: OUT_REG ref: ad_iob28 mod: OUT_REG ref: ad_iob29 mod: OUT_REG ref: ad_iob3 mod: OUT_REG ref: ad_iob30 mod: OUT_REG ref: ad_iob31 mod: OUT_REG ref: ad_iob4 mod: OUT_REG ref: ad_iob5 mod: OUT_REG ref: ad_iob6 mod: OUT_REG ref: ad_iob7 mod: OUT_REG ref: ad_iob8 mod: OUT_REG ref: ad_iob9 mod: PCI_IO_MUX_AD_LOAD_CRIT ref: ad_load_high_gen mod: PCI_IO_MUX_AD_LOAD_CRIT ref: ad_load_low_gen mod: PCI_IO_MUX_AD_LOAD_CRIT ref: ad_load_mhigh_gen mod: PCI_IO_MUX_AD_LOAD_CRIT ref: ad_load_mlow_gen mod: OUT_REG ref: cbe_iob0 mod: OUT_REG ref: cbe_iob1 mod: OUT_REG ref: cbe_iob2 mod: OUT_REG ref: cbe_iob3 mod: OUT_REG ref: devsel_iob mod: OUT_REG ref: frame_iob mod: OUT_REG ref: irdy_iob mod: OUT_REG ref: par_iob mod: OUT_REG ref: perr_iob mod: OUT_REG ref: req_iob mod: OUT_REG ref: serr_iob mod: OUT_REG ref: stop_iob mod: OUT_REG ref: trdy_iob module: PCI_IO_MUX_AD_EN_CRIT module: PCI_IO_MUX_AD_LOAD_CRIT module: PCI_TARGET32_SM mod: PCI_TARGET32_CLK_EN ref: pci_target_clock_en mod: PCI_TARGET32_DEVS_CRIT ref: pci_target_devsel_critical mod: PCI_TARGET32_STOP_CRIT ref: pci_target_stop_critical mod: PCI_TARGET32_TRDY_CRIT ref: pci_target_trdy_critical module: SERR_EN_CRIT module: DELAYED_WRITE_REG module: MAS_AD_EN_CRIT module: MAS_AD_LOAD_CRIT module: PCI_MASTER32_SM mod: MAS_AD_EN_CRIT ref: ad_iob_oe_feed mod: CBE_EN_CRIT ref: cbe_iob_feed mod: FRAME_LOAD_CRIT ref: frame_iob_ce mod: FRAME_EN_CRIT ref: frame_iob_en_feed mod: FRAME_CRIT ref: frame_iob_feed mod: IRDY_OUT_CRIT ref: irdy_iob_feed mod: MAS_AD_LOAD_CRIT ref: mas_ad_load_feed mod: MAS_CH_STATE_CRIT ref: state_machine_ce module: PCI_TARGET32_STOP_CRIT module: synchronizer_flop module: async_reset_flop module: MAS_CH_STATE_CRIT module: PCI_TARGET32_TRDY_CRIT module: TOP mod: bufif1 ref: AD_buf0 mod: bufif1 ref: AD_buf1 mod: bufif1 ref: AD_buf10 mod: bufif1 ref: AD_buf11 mod: bufif1 ref: AD_buf12 mod: bufif1 ref: AD_buf13 mod: bufif1 ref: AD_buf14 mod: bufif1 ref: AD_buf15 mod: bufif1 ref: AD_buf16 mod: bufif1 ref: AD_buf17 mod: bufif1 ref: AD_buf18 mod: bufif1 ref: AD_buf19 mod: bufif1 ref: AD_buf2 mod: bufif1 ref: AD_buf20 mod: bufif1 ref: AD_buf21 mod: bufif1 ref: AD_buf22 mod: bufif1 ref: AD_buf23 mod: bufif1 ref: AD_buf24 mod: bufif1 ref: AD_buf25 mod: bufif1 ref: AD_buf26 mod: bufif1 ref: AD_buf27 mod: bufif1 ref: AD_buf28 mod: bufif1 ref: AD_buf29 mod: bufif1 ref: AD_buf3 mod: bufif1 ref: AD_buf30 mod: bufif1 ref: AD_buf31 mod: bufif1 ref: AD_buf4 mod: bufif1 ref: AD_buf5 mod: bufif1 ref: AD_buf6 mod: bufif1 ref: AD_buf7 mod: bufif1 ref: AD_buf8 mod: bufif1 ref: AD_buf9 mod: bufif1 ref: CBE_buf0 mod: bufif1 ref: CBE_buf1 mod: bufif1 ref: CBE_buf2 mod: bufif1 ref: CBE_buf3 mod: bufif1 ref: DEVSEL_buf mod: bufif1 ref: FRAME_buf mod: bufif1 ref: INTA_buf mod: bufif1 ref: IRDY_buf mod: bufif1 ref: PAR_buf mod: bufif1 ref: PERR_buf mod: bufif1 ref: REQ_buf mod: bufif1 ref: RST_buf mod: bufif1 ref: SERR_buf mod: bufif1 ref: STOP_buf mod: bufif1 ref: TRDY_buf mod: PCI_BRIDGE32 ref: bridge module: PCI_RST_INT mod: OUT_REG ref: inta module: SYNC_MODULE mod: synchronizer_flop ref: clear_delete_sync mod: synchronizer_flop ref: delete_sync module: WB_TPRAM mod: RAM16X1D ref: ram00 mod: RAM16X1D ref: ram01 mod: RAM16X1D ref: ram02 mod: RAM16X1D ref: ram03 mod: RAM16X1D ref: ram04 mod: RAM16X1D ref: ram05 mod: RAM16X1D ref: ram06 mod: RAM16X1D ref: ram07 mod: RAM16X1D ref: ram08 mod: RAM16X1D ref: ram09 mod: RAM16X1D ref: ram10 mod: RAM16X1D ref: ram11 mod: RAM16X1D ref: ram12 mod: RAM16X1D ref: ram13 mod: RAM16X1D ref: ram14 mod: RAM16X1D ref: ram15 mod: RAM16X1D ref: ram16 mod: RAM16X1D ref: ram17 mod: RAM16X1D ref: ram18 mod: RAM16X1D ref: ram19 mod: RAM16X1D ref: ram20 mod: RAM16X1D ref: ram21 mod: RAM16X1D ref: ram22 mod: RAM16X1D ref: ram23 mod: RAM16X1D ref: ram24 mod: RAM16X1D ref: ram25 mod: RAM16X1D ref: ram26 mod: RAM16X1D ref: ram27 mod: RAM16X1D ref: ram28 mod: RAM16X1D ref: ram29 mod: RAM16X1D ref: ram30 mod: RAM16X1D ref: ram31 mod: RAM16X1D ref: ram32 mod: RAM16X1D ref: ram33 mod: RAM16X1D ref: ram34 mod: RAM16X1D ref: ram35 mod: RAM16X1D ref: ram36 mod: RAM16X1D ref: ram37 mod: RAM16X1D ref: ram38 mod: RAM16X1D ref: ram39 mod: RAMB4_S16_S16 ref: ramb4_s16_s16_1 mod: RAMB4_S16_S16 ref: ramb4_s16_s16_2 module: WB_MASTER32 module: WB_MASTER_BEHAVIORAL mod: WB_MASTER32 ref: wbm_low_level module: SYSTEM mod: TOP ref: `PCI_BRIDGE_INSTANCE mod: PCI_BEHAVIORAL_IACK_TARGET ref: interrupt_control mod: pci_unsupported_commands_master ref: ipci_unsupported_commands_master mod: pullup ref: lockpu mod: pci_bus_monitor ref: monitor32 mod: pci_blue_arbiter ref: pci_arbiter mod: pci_behaviorial_device ref: pci_behaviorial_device1 mod: pci_behaviorial_device ref: pci_behaviorial_device2 mod: WB_BUS_MON ref: pciu_wb_mon mod: WB_BUS_MON ref: wbu_wb_mon mod: WB_MASTER_BEHAVIORAL ref: wishbone_master mod: WB_SLAVE_BEHAVIORAL ref: wishbone_slave module: pci_blue_arbiter module: pci_bus_monitor module: pci_behaviorial_device mod: pci_behaviorial_master ref: pci_behaviorial_master mod: pci_behaviorial_target ref: pci_behaviorial_target mod: delayed_test_pad ref: test_pad_devsel mod: delayed_test_pad ref: test_pad_frame mod: delayed_test_pad ref: test_pad_idsel mod: delayed_test_pad ref: test_pad_irdy mod: delayed_test_pad ref: test_pad_par mod: delayed_test_pad ref: test_pad_perr mod: delayed_test_pad ref: test_pad_serr mod: delayed_test_pad ref: test_pad_stop mod: delayed_test_pad ref: test_pad_trdy module: delayed_test_pad module: pci_behaviorial_master module: pci_behaviorial_target module: WB_SLAVE_BEHAVIORAL module: WB_BUS_MON module: PCI_BEHAVIORAL_IACK_TARGET module: pci_unsupported_commands_master module: REPORT_end task list Assert_DEVSEL Assert_FRAME Assert_IRDY Assert_Master_Continue_Or_Terminate Assert_STOP Assert_TRDY Assert_Target_Continue_Or_Disconnect Capture_Config_Reg_Data_From_AD_Bus Capture_SRAM_Data_From_AD_Bus Check_Master_Abort_Counter Check_Master_Burst_Termination_Cause Check_Target_Abort Check_Target_Retry Check_Target_Stop Clock_Wait_Unless_Reset Clock_Wait_Unless_Reset Compare_Read_Data_With_Expected_Data Complain_That_Test_Not_Written DO_REF Deassert_DEVSEL Deassert_FRAME Deassert_IRDY Deassert_STOP Deassert_TRDY Execute_Master_PCI_Ref Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B Execute_Master_Waitstates_But_Quit_On_Target_Abort Execute_Target_Abort_Undrive_DEVSEL Execute_Target_PCI_Ref Execute_Target_Ref_Undrive_DEVSEL_On_Any_Termination Execute_Target_Retry_Undrive_DEVSEL Execute_Target_Waitstates Fetch_Config_Reg_Data_For_Read_Onto_AD_Bus Fetch_SRAM_Data_For_Read_Onto_AD_Bus Inc_Master_Abort_Counter Indicate_Done Indicate_Start Init_Master_Abort_Counter Init_Test_Device_SRAM Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort Linger_Until_Master_Waitstates_Done Linger_Until_Target_Waitstates_Done Master_Assert_Address Master_Req_Bus Master_Unreq_Bus PCIU_CONFIG_READ PCIU_CONFIG_READ_MASTER_ABORT PCIU_CONFIG_WRITE PCIU_CONFIG_WRITE_MASTER_ABORT PCIU_IO_READ PCIU_IO_READ_MAKE_PERR PCIU_IO_WRITE PCIU_IO_WRITE_MAKE_PERR PCIU_MEM_READ PCIU_MEM_READ_LN PCIU_MEM_READ_MAKE_PERR PCIU_MEM_READ_MASTER_ABORT PCIU_MEM_READ_MUL PCIU_MEM_WRITE PCIU_MEM_WRITE_MAKE_PERR PCIU_MEM_WRITE_MAKE_SERR PCIU_MEM_WRITE_MASTER_ABORT PCIU_READ Read_Test_Device_Config_Regs Read_Test_Device_SRAM Report_Master_Reference_Paramaters Report_On_Master_PCI_Ref_Finish Report_On_Master_PCI_Ref_Start Report_On_Target_PCI_Ref_Start Report_Target_Reference_Paramaters Reset_Master_To_Idle Reset_Target_To_Idle Update_Write_Data Wait_Till_DEVSEL_Possible Watch_For_Back_To_Back_Drive_Of_OE_Sigs Watch_For_Deassert_Before_Tristate Watch_For_Simultaneous_Drive_Of_OE_Sigs Watch_For_X_On_OE_Sigs Write_Test_Device_Config_Regs Write_Test_Device_SRAM config_read config_write configuration_cycle_read configure_bridge_target_base_addresses cycle_response display_warning do_reference do_reset end_cycle fill_memory find_device find_pci_devices iack_cycle master_reference modify_cycle musnt_respond parity_checking pci_transaction_progress_monitor run_tests start_cycle target_completion_expiration target_disconnects target_fast_back_to_back target_unsupported_cmds test_fail test_normal_wr_rd test_pci_image test_summary test_target_abort test_target_io_err_wr test_target_io_wr_rd test_wb_error_rd test_wb_error_wr test_wb_image transaction_ordering wb_RMW_read wb_RMW_write wb_block_read wb_block_write wb_single_read wb_single_write wb_slave_errors wb_to_pci_transactions wb_transaction_progress_monitor wb_transaction_progress_monitor_backup wb_transaction_stop wbm_read wbm_write function list Pinhas and Beatris Krengel Tel : (also voice mail and fax) 972-9-8947865 Portable : 972-54-679119 Portable: 972-54-649119 Chat with friends online, try MSN Messenger: Click Here |
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hierarchy of the design
by Unknown on Jan 19, 2004 |
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>>>>> "nishachamp" == nishachamp nishachamp@yahoo.com> writes:
nishachamp> We cant seem to be able to finf the module definition for
nishachamp> RAMB4_S16_S16 as well as RAM16X1D. Kindly assist.
You need to include the Xilinx verilog/unisims directory if you want to
compile for Xilinx. For other architectures, things may vary.
nishachamp> --Nisha
nishachamp> ----- Original Message ----- From: "PinhasNBeatris Krengel"
Please don't fullquote!
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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