Hello Folks, I'm moving a project with the pci core from the ISE 4.1i tool to the newer ISE 6.1i tool. It now seems that no matter what I do, the tools will not place the output registers in pci_out_reg.v into the IOBs of the FPGA. I've specified the IOB constraint in both the UCF file and in the verilog code itself with no luck. It appears that since these registers are not declared at the top level of the project hierarchy, the IOB constraint is ignored. Does anyone have a work around for this? Thanks very much, Charles -- Charles Martin "It is a very sad thing that nowadays Test & Measurement Systems there is so little useless information" Charles_Martin@tamsinc.com --- Oscar Wilde (970) 669 6553 ext. 16