Hi, We would like to synthesize and implement pci_crt or pci bridge only application. I am new to opencores pci bridge and verilog. I am not sure how to setup the project. I started with pci_crt. I am using Xilinx Foundation F3.1i with FPGA Express ver 3.5. I added all source files from pci/rtl/verilog directory (with exeption of pci_wbs_wbb3_2wbb2.v) next all source files from pci/apps/crt/rtl/verilog directory. After synthesis I have two files: top.edf and top.ncf. My understanding is that ngdbuild will take top.edf to produce .ngd file. Directory structure is: c:\opencores\ucf\pci_crt.ucf - from pci\apps\crt\syn\ucf c:\opencores\pci_crt\top.edf and .ncf - after synthesis c:\opencores\scr\run.bat - script file with ngdbuild C:\opencores\scr>ngdbuild -p xc2s150-5-pq208 -uc ..\ucf\pci_crt.ucf -dd ..\pci_crt\top.edf pci_crt.ngd I am receiving following error message. Release 3.3.08i - ngdbuild D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -p xc2s150-5-pq208 -uc ..\ucf\pci_crt.ucf -dd ..\pci_crt\top.edf pci_crt.ngd ERROR:NgdBuild:25 - Cannot both read and write file "pci_crt.ngd"! Please specify a file other than the destination NGD file as the top-level input design file.One or more errors were found during NGDBUILD. No NGD file will be written.Writing NGDBUILD log file "pci_crt.bld"... Please let me know where is possible problem. Thank you for any help. Regards, Richard -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/pci/attachments/20040201/76faae44/attachment.htm