Hi everyone,

While i am reading the PCI specification 2.2, in table 6-1 which is talking
about the bits in the command register in the configuration space. For
bit 0 it says "State after RST# is 0." Bit 0 is the control of response to
the IO space access. If my device support IO space access , i just
hardcode a "1" in this bit, i don't understan why the specification says
state after RST is 0. Can anybody help me?



Regards,
TOM