Hi, We would like to synthesize and implement pci_crt or pci bridge only application. I am new to opencores pci bridge and verilog. I am not sure how to setup the project. I started with pci_crt. I am using WebPack 6.1i. pci_crt project file ..\apps\crt\syn\webpack\ise_openpci was created with ver 5. I am receiving following error message: "Source file ..\apps\crt\verilog\top.v does not exist.". File exist and message does not make any sense. Any information would be greatly appreciated! Regards, Richard -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/pci/attachments/20040203/4cb46d7a/attachment.htm