Hi,

I had a question regarding the implementation of your PCI Core in a 66
MHz PCI bus application. I am using a Virtex E device and have used
your core as the PCI bridge.
The problem is that I am not able to meet the PCI input timing
specifications (3 ns pad to setup), probably because all the PCI signals
are not registered before being used in your PCI bridge.

Can you suggest how I can modify the constraints or the Core to
achieve this?

Also, has your PCI bridge been used in a 66 MHZ application, if yes, how
did you meet the PCI input timing specifications.

Thanking you in advance.

Regards,
Abhishek.