OpenCores

OpenCores

Problem with bandwidth

no use

no use

1/1

no use

no use

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine. Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine.

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
BROTO Laurent wrote: [q] My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs.[/q] The PCI bus is asymmetrical: master writings are fastest than slave readings... [q] I think 300 Âµs to write to bus is too slow.[/q] You said 300us for readings, not for writings :-) If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD. I hope this help. Bye. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) BROTO Laurent wrote: My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. The PCI bus is asymmetrical: master writings are fastest than slave readings... I think 300 Âµs to write to bus is too slow. You said 300us for readings, not for writings :-) If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD. I hope this help. Bye. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III)

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Marco Buffa wrote: [q] BROTO Laurent wrote: [q] I think 300 Âµs to write to bus is too slow.[/q] You said 300us for readings, not for writings :-)[/q] You're right, sorry :-) [q] If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD. [/q] Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ? Have you got a solution ? Thanks a lot, -- Laurent Marco Buffa wrote: BROTO Laurent wrote: I think 300 Âµs to write to bus is too slow. You said 300us for readings, not for writings :-) You're right, sorry :-) If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD. Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ? Have you got a solution ? Thanks a lot, -- Laurent

Problem with bandwidth by AustinFranklin on Mar 15, 2004			AustinFranklin Posts: 17 Joined: Sep 12, 2008 Last seen: Jan 26, 2021
[q]> My problem is following: when I read 4ko from PCI bus, it take[/q] about 300 [q]> Âµs (microseconds). When I write to PCI bus, it take about 20Âµs.[/q] The PCI bus is asymmetrical: master writings are fastest than slave readings...[/q] With respect to the PCI bus, this not correct. The PCI bus protocol, in and of it self, is not asymmetrical. Every transaction is initiated by a master, and received by a slave, write or read. The transaction protocol is identical for every master/slave. I'm not sure what you mean by "slave reading", the slave may be read from, but not initiate the read. Of course, there may be an implementation difference (which is what I think you are referring to) such as system is master and reading from the board is slow because CPU is doing the transfer, and board master and reading from system is fast...etc., but that has nothing to do with the PCI protocol, and does not make the protocol asymmetrical. [q]> I think 300 Âµs to write to bus is too slow.[/q] You said 300us for readings, not for writings :-) If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD.[/q] It appears in his case that all his transactions are CPU generated (wasn't stated)...which is typically quite slow. Of course, as I believe you are saying here, using an on-board master to initiate the transfers is typically much faster than doing the transfer using the CPU to initiate it. Regards, Austin > My problem is following: when I read 4ko from PCI bus, it take about 300 > Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. The PCI bus is asymmetrical: master writings are fastest than slave readings... With respect to the PCI bus, this not correct. The PCI bus protocol, in and of it self, is not asymmetrical. Every transaction is initiated by a master, and received by a slave, write or read. The transaction protocol is identical for every master/slave. I'm not sure what you mean by "slave reading", the slave may be read from, but not initiate the read. Of course, there may be an implementation difference (which is what I think you are referring to) such as system is master and reading from the board is slow because CPU is doing the transfer, and board master and reading from system is fast...etc., but that has nothing to do with the PCI protocol, and does not make the protocol asymmetrical. > I think 300 Âµs to write to bus is too slow. You said 300us for readings, not for writings :-) If you want to increase the transfer rate, you must _write_ from the BOARD to PC (DMA mode), not _read_ from the BOARD. It appears in his case that all his transactions are CPU generated (wasn't stated)...which is typically quite slow. Of course, as I believe you are saying here, using an on-board master to initiate the transfers is typically much faster than doing the transfer using the CPU to initiate it. Regards, Austin

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
BROTO Laurent wrote: [q] Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ?[/q] No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) BROTO Laurent wrote: Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ? No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III)

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Austin Franklin wrote: [q]The PCI bus is asymmetrical: master writings are fastest than slave readings...[/q] With respect to the PCI bus, this not correct. The PCI bus protocol, in and of it self, is not asymmetrical. Every transaction is initiated by a master, and received by a slave, write or read. The transaction protocol is identical for every master/slave. I'm not sure what you mean by "slave reading", the slave may be read from, but not initiate the read.[/q] Ok, you are right, I would like to mean that, but I'm not very familiar with english :-( [q] Of course, there may be an implementation difference (which is what I think you are referring to)[/q] That's exact, thank's! Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) Austin Franklin wrote: The PCI bus is asymmetrical: master writings are fastest than slave readings... With respect to the PCI bus, this not correct. The PCI bus protocol, in and of it self, is not asymmetrical. Every transaction is initiated by a master, and received by a slave, write or read. The transaction protocol is identical for every master/slave. I'm not sure what you mean by "slave reading", the slave may be read from, but not initiate the read. Ok, you are right, I would like to mean that, but I'm not very familiar with english :-( Of course, there may be an implementation difference (which is what I think you are referring to) That's exact, thank's! Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III)

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Marco Buffa wrote: [q] BROTO Laurent wrote: [q] Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ?[/q] No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards.[/q] Thanks a lot, I'll try this solution. Regards Marco Buffa wrote: BROTO Laurent wrote: Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ? No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards. Thanks a lot, I'll try this solution. Regards

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Is there anyone who has written such a DMA capable driver (for Linux)? Or maybe changed/adapted spartan_drv.c? Regards/Nico. -----Original Message----- From: Marco Buffa [mailto:<A HREF="mailto:marcobuffa@lombardiacom.it">marcobuffa@lombardiacom.it</A>] Sent: Monday, March 15, 2004 4:47 PM To: Discussion list about free, open source PCI IP core Subject: Re: [pci] Problem with bandwidth BROTO Laurent wrote: [q] Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ?[/q] No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/pci">http://www.opencores.org/mailman/listinfo/pci</A> This communication is confidential and intended solely for the addressee(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you believe this message has been sent to you in error, please notify the sender by replying to this transmission and delete the message without disclosing it. Thank you. E-mail including attachments is susceptible to data corruption, interruption, unauthorized amendment, tampering and viruses, and we only send and receive e-mails on the basis that we are not liable for any such corruption, interception, amendment, tampering or viruses or any consequences thereof. Is there anyone who has written such a DMA capable driver (for Linux)? Or maybe changed/adapted spartan_drv.c? Regards/Nico. -----Original Message----- From: Marco Buffa [mailto:marcobuffa@lombardiacom.it] Sent: Monday, March 15, 2004 4:47 PM To: Discussion list about free, open source PCI IP core Subject: Re: [pci] Problem with bandwidth BROTO Laurent wrote: Ok, but how can I do this ? Should I set my core as HOST ? And if I set my core as HOST, what's about writting ? No, I suppose your PCI host is already in your PC :-) You need to add a master capable WB unit to your core, connecting it to the WB slave unit of the PCI core. When your WB master unit will write to PCI core slave WB unit, the PCI core will generate a master access to the PCI bus. Of course you need to write a DMA capable device driver for the board. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) _______________________________________________ http://www.opencores.org/mailman/listinfo/pci This communication is confidential and intended solely for the addressee(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you believe this message has been sent to you in error, please notify the sender by replying to this transmission and delete the message without disclosing it. Thank you. E-mail including attachments is susceptible to data corruption, interruption, unauthorized amendment, tampering and viruses, and we only send and receive e-mails on the basis that we are not liable for any such corruption, interception, amendment, tampering or viruses or any consequences thereof.

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Nico Weling (AC/EED) wrote: [q] Is there anyone who has written such a DMA capable driver (for Linux)? Or maybe changed/adapted spartan_drv.c?[/q] I would like to write one, and I started to work on it during my thesis, but I suspended the project 'cause now I'm very busy with my work :-( Note that a dma capable driver is "WB master dependent", so maybe my driver will work correctly for my WB fsm, but not for other ones :-( Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) Nico Weling (AC/EED) wrote: Is there anyone who has written such a DMA capable driver (for Linux)? Or maybe changed/adapted spartan_drv.c? I would like to write one, and I started to work on it during my thesis, but I suspended the project 'cause now I'm very busy with my work :-( Note that a dma capable driver is "WB master dependent", so maybe my driver will work correctly for my WB fsm, but not for other ones :-( Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III)

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Hi Marco, [q]Note that a dma capable driver is "WB master dependent", so maybe my driver will work correctly for my WB fsm, but not for other ones :-([/q] That's right, but it would be a good starting point ;-) Regards/Nico. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 <A HREF="mailto:marcobuffa@jabber.linux.it">marcobuffa@jabber.linux.it</A> <A HREF="http://marcobuffa.altervista.org">http://marcobuffa.altervista.org</A> "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/pci">http://www.opencores.org/mailman/listinfo/pci</A> This communication is confidential and intended solely for the addressee(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you believe this message has been sent to you in error, please notify the sender by replying to this transmission and delete the message without disclosing it. Thank you. E-mail including attachments is susceptible to data corruption, interruption, unauthorized amendment, tampering and viruses, and we only send and receive e-mails on the basis that we are not liable for any such corruption, interception, amendment, tampering or viruses or any consequences thereof. Hi Marco, Note that a dma capable driver is "WB master dependent", so maybe my driver will work correctly for my WB fsm, but not for other ones :-( That's right, but it would be a good starting point ;-) Regards/Nico. Regards. -- Marco Buffa (FZS600'01) Laboratorio di Spettroscopia Digitale Dipartimento di Elettronica - Politecnico di Milano tel. +39-02-2399-4004 marcobuffa@jabber.linux.it http://marcobuffa.altervista.org "Scorrelare vuol dire smarmellare." (prof. Franco Zappa, Lezione di elettronica III) _______________________________________________ http://www.opencores.org/mailman/listinfo/pci This communication is confidential and intended solely for the addressee(s). Any unauthorized review, use, disclosure or distribution is prohibited. If you believe this message has been sent to you in error, please notify the sender by replying to this transmission and delete the message without disclosing it. Thank you. E-mail including attachments is susceptible to data corruption, interruption, unauthorized amendment, tampering and viruses, and we only send and receive e-mails on the basis that we are not liable for any such corruption, interception, amendment, tampering or viruses or any consequences thereof.

Problem with bandwidth by Unknown on Mar 15, 2004			Not available!
Hello guys, I have some experiences on the PCI bandwidth. Let me explain my experience a little longer. I have designed and implemented a PCI board using Xilinx FPGA. The PCI core is bought from Xilinx. And the board is bought from Insight. The PCI core from Xilinx is really simple, actually it just translated the PCI protocol to some Xilinx defined local bus protocol, although still really like the PCI interface. The good thing is you don't have to bouther about the PC boot up sequence and configuration. The bad thing is actually you need to design everything yourself to implement either the slave or the master mode of your board. Yes, PCI 33 has the bandwith up to 33MHz x 4 bytes. But to reach that speed, you must design your board to be in PCI master mode and could do burst mode transfer to and from PC main memory via PCI bus. Also, your driver, no matter Linux driver or Windoz driver, must also be able to initialize your board's master mode. My board works in the following flow (writing to PC memory): 1. it first sample data from some data source and save these data into a FIFO. 2. When the FIFO has reached some threshold, say 3/4 full, it will request a PCI master write request to PCI arbitor. 3. When he gets the grant from the PCI bus arbitor, it begin to write data to PC memory in burst mode via PCI bus. At this time, my board is the PCI master, and the PC memory looks like a PCI slave. 4. When finished the transfer, release the PCI bus. In your case in which speed is only 300us, I think maybe your board is not in burst mode. You can use scope or FPGA chipscope (sorry, I don't what's the Altera's counterpart) to sample the PCI bus to see what is really happening. And remember, to be in burst mode, both the driver and PCI board should be configured properly. If any questions, please feel free to contact me. My email address is <A HREF="mailto:mengjt@yahoo.com">mengjt@yahoo.com</A> Hello guys, I have some experiences on the PCI bandwidth. Let me explain my experience a little longer. I have designed and implemented a PCI board using Xilinx FPGA. The PCI core is bought from Xilinx. And the board is bought from Insight. The PCI core from Xilinx is really simple, actually it just translated the PCI protocol to some Xilinx defined local bus protocol, although still really like the PCI interface. The good thing is you don't have to bouther about the PC boot up sequence and configuration. The bad thing is actually you need to design everything yourself to implement either the slave or the master mode of your board. Yes, PCI 33 has the bandwith up to 33MHz x 4 bytes. But to reach that speed, you must design your board to be in PCI master mode and could do burst mode transfer to and from PC main memory via PCI bus. Also, your driver, no matter Linux driver or Windoz driver, must also be able to initialize your board's master mode. My board works in the following flow (writing to PC memory): 1. it first sample data from some data source and save these data into a FIFO. 2. When the FIFO has reached some threshold, say 3/4 full, it will request a PCI master write request to PCI arbitor. 3. When he gets the grant from the PCI bus arbitor, it begin to write data to PC memory in burst mode via PCI bus. At this time, my board is the PCI master, and the PC memory looks like a PCI slave. 4. When finished the transfer, release the PCI bus. In your case in which speed is only 300us, I think maybe your board is not in burst mode. You can use scope or FPGA chipscope (sorry, I don't what's the Altera's counterpart) to sample the PCI bus to see what is really happening. And remember, to be in burst mode, both the driver and PCI board should be configured properly. If any questions, please feel free to contact me. My email address is mengjt@yahoo.com

Problem with bandwidth by Unknown on Mar 18, 2004			Not available!
BROTO Laurent wrote: [q] Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/pci">http://www.opencores.org/mailman/listinfo/pci</A> [/q] Thanks to all. I've built a bus master engine and all work fine. I've got now two interrupts: - first: 10 us, - second: 10 us. The transfert take about 50 us but my processor is free during this time. Regards, -- Laurent BROTO Laurent wrote: Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine. _______________________________________________ http://www.opencores.org/mailman/listinfo/pci Thanks to all. I've built a bus master engine and all work fine. I've got now two interrupts: - first: 10 us, - second: 10 us. The transfert take about 50 us but my processor is free during this time. Regards, -- Laurent

Problem with bandwidth by Unknown on Mar 22, 2004			Not available!
Hi, Sorry for any inconvenience; I see that you use Altera's FPGA, and perhaps you can help me. I'm using the Opencores PCI bridge for an Firewire application, with an Altera Apex FPGA and NIOS processor.I'm using the the Host configuration of the bridge; before make proves with the PCI side of the bridge, i'm attempt read the PCI configuration space header (00h to 3Ch), but have the following problem: after read the fixe registers of this space i'm obtain the values (Device, vendor,...) in a mess!! You has have a similar problems? can help me? Thanks and sorry to disturb you. [q]===== Original Message From "Discussion list about free, open source PCI IP[/q] core" <<A HREF="mailto:pci@opencores.org">pci@opencores.org</A>> ===== [q]BROTO Laurent wrote: [q] Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/pci">http://www.opencores.org/mailman/listinfo/pci</A> [/q] Thanks to all. I've built a bus master engine and all work fine. I've got now two interrupts: - first: 10 us, - second: 10 us. The transfert take about 50 us but my processor is free during this time. Regards, -- Laurent _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/pci">http://www.opencores.org/mailman/listinfo/pci</A>[/q] jose maria illa Hi, Sorry for any inconvenience; I see that you use Altera's FPGA, and perhaps you can help me. I'm using the Opencores PCI bridge for an Firewire application, with an Altera Apex FPGA and NIOS processor.I'm using the the Host configuration of the bridge; before make proves with the PCI side of the bridge, i'm attempt read the PCI configuration space header (00h to 3Ch), but have the following problem: after read the fixe registers of this space i'm obtain the values (Device, vendor,...) in a mess!! You has have a similar problems? can help me? Thanks and sorry to disturb you. ===== Original Message From "Discussion list about free, open source PCI IP core" pci@opencores.org> ===== BROTO Laurent wrote: Hi, I'm using PCI opencores core in my application. My FPGA is an ALTERA Cyclone and I haven't any problem with time constraints. I wrote a driver for linux to use this board. My problem is following: when I read 4ko from PCI bus, it take about 300 Âµs (microseconds). When I write to PCI bus, it take about 20Âµs. I think 300 Âµs to write to bus is too slow. Can you confirm this ? And if it's really to slow, have you got an idea to speed up the write cycle ? Regards, -- BROTO Laurent In my pci_user_constants, I've defined: - GUEST, - Two memory images with 14 lines to decode. To read from PCI bus, I use a memcpy routine. _______________________________________________ http://www.opencores.org/mailman/listinfo/pci Thanks to all. I've built a bus master engine and all work fine. I've got now two interrupts: - first: 10 us, - second: 10 us. The transfert take about 50 us but my processor is free during this time. Regards, -- Laurent _______________________________________________ http://www.opencores.org/mailman/listinfo/pci jose maria illa

Problem with bandwidth by Unknown on Mar 23, 2004			Not available!
JosÃ© MarÃa Illa Laguna wrote: [q]Hi, Sorry for any inconvenience; I see that you use Altera's FPGA, and perhaps you can help me. I'm using the Opencores PCI bridge for an Firewire application, with an Altera Apex FPGA and NIOS processor.I'm using the the Host configuration of the bridge; before make proves with the PCI side of the bridge, i'm attempt read the PCI configuration space header (00h to 3Ch), but have the following problem: after read the fixe registers of this space i'm obtain the values (Device, vendor,...) in a mess!! You has have a similar problems? can help me? Thanks and sorry to disturb you. [/q] Yes, I'm using an ALETRA's Cyclone FPGA but I don't use NIOS processor. My bridge is configured as GUEST and no HOST. So I can't help you because I don't know about HOST configuration cycle. But if you receive values in a mess, try to deal with little endian and big endian. Good luck, -- Laurent JosÃ© MarÃa Illa Laguna wrote: Hi, Sorry for any inconvenience; I see that you use Altera's FPGA, and perhaps you can help me. I'm using the Opencores PCI bridge for an Firewire application, with an Altera Apex FPGA and NIOS processor.I'm using the the Host configuration of the bridge; before make proves with the PCI side of the bridge, i'm attempt read the PCI configuration space header (00h to 3Ch), but have the following problem: after read the fixe registers of this space i'm obtain the values (Device, vendor,...) in a mess!! You has have a similar problems? can help me? Thanks and sorry to disturb you. Yes, I'm using an ALETRA's Cyclone FPGA but I don't use NIOS processor. My bridge is configured as GUEST and no HOST. So I can't help you because I don't know about HOST configuration cycle. But if you receive values in a mess, try to deal with little endian and big endian. Good luck, -- Laurent

no use

no use

1/1

no use

no use

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.