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WB slave(PCI master) wirte its value to the next address
by Unknown on Mar 19, 2004 		Not available!
Hi,
I'm upgrading our VME bridge which uses the Opencore's pci core.
I found a very strange problem.
When the PCI bus is busy and read and write operation is repeated on
WISHBONE bus side.
Some times the write value is written to the next address of it's
destination.
To test the phenominan I excuted the following code repeatedly.

*(volatile unsigned int*)adrs = adrs; //Write value
value = *(volatile unsigned int*)(adrs+4); // Read value of the next
address
if (value == (unsigned int)addr) // If the value is same as
adrs print error message
printf ("Error at %08lx : %08x\n", (unsigned long)(adrs+4), value);

As you can see the error message should never be appeared.
But it is sometimes appeared when the PCI bus is busy.
Does anyone in this list had the problem?

Regards,
Sangmoon Kim

WB slave(PCI master) wirte its value to the next address
by Unknown on Mar 19, 2004 		Not available!
Hi! I've got one report of exactly the same thing, but I was not able to locate it within the simulation. Your bit of code gives me a good starting point for the testcase. I'll test that as soon as I can. Can you tell me a bit more about your environment - fifo sizes, wb clock period, pci clock period .... Regards, Miha Dolenc ----- Original Message ----- From: "Sangmoon Kim" dogoil@etinsys.com> To: pci@opencores.org> Sent: Friday, March 19, 2004 8:27 AM Subject: [pci] WB slave(PCI master) wirte its value to the next address
Hi,
I'm upgrading our VME bridge which uses the Opencore's pci core.
I found a very strange problem.
When the PCI bus is busy and read and write operation is repeated on
WISHBONE bus side.
Some times the write value is written to the next address of it's
destination.
To test the phenominan I excuted the following code repeatedly.

*(volatile unsigned int*)adrs = adrs; //Write value
value = *(volatile unsigned int*)(adrs+4); // Read value of the next
address
if (value == (unsigned int)addr) // If the value is same

as
adrs print error message
printf ("Error at %08lx : %08x\n", (unsigned long)(adrs+4),

value);
As you can see the error message should never be appeared. But it is sometimes appeared when the PCI bus is busy. Does anyone in this list had the problem? Regards, Sangmoon Kim _______________________________________________ http://www.opencores.org/mailman/listinfo/pci



WB slave(PCI master) wirte its value to the next address
by Unknown on Mar 19, 2004 		Not available!
Hi! I think I finally caught it. Can you please update your rtl/verilog/pci_master32_sm_if.v run your test again and let me know what are the results? Regards, Miha Dolenc ----- Original Message ----- From: "Sangmoon Kim" dogoil@etinsys.com> To: pci@opencores.org> Sent: Friday, March 19, 2004 8:27 AM Subject: [pci] WB slave(PCI master) wirte its value to the next address
Hi,
I'm upgrading our VME bridge which uses the Opencore's pci core.
I found a very strange problem.
When the PCI bus is busy and read and write operation is repeated on
WISHBONE bus side.
Some times the write value is written to the next address of it's
destination.
To test the phenominan I excuted the following code repeatedly.

*(volatile unsigned int*)adrs = adrs; //Write value
value = *(volatile unsigned int*)(adrs+4); // Read value of the next
address
if (value == (unsigned int)addr) // If the value is same

as
adrs print error message
printf ("Error at %08lx : %08x\n", (unsigned long)(adrs+4),

value);
As you can see the error message should never be appeared. But it is sometimes appeared when the PCI bus is busy. Does anyone in this list had the problem? Regards, Sangmoon Kim _______________________________________________ http://www.opencores.org/mailman/listinfo/pci



WB slave(PCI master) wirte its value to the next address
by Unknown on Mar 23, 2004 		Not available!
Hi, Thank you very much. It really solves the problem. Regards, Sangmoon Kim ----- Original Message ----- From: "Miha Dolenc" mihad@opencores.org> To: "Discussion list about free,open source PCI IP core" pci@opencores.org> Sent: Saturday, March 20, 2004 2:29 AM Subject: Re: [pci] WB slave(PCI master) wirte its value to the next address
Hi! I think I finally caught it. Can you please update your rtl/verilog/pci_master32_sm_if.v run your test again and let me know what are the results? Regards, Miha Dolenc ----- Original Message ----- From: "Sangmoon Kim" dogoil@etinsys.com> To: pci@opencores.org> Sent: Friday, March 19, 2004 8:27 AM Subject: [pci] WB slave(PCI master) wirte its value to the next address
> Hi,
> I'm upgrading our VME bridge which uses the Opencore's pci core.
> I found a very strange problem.
> When the PCI bus is busy and read and write operation is repeated on
> WISHBONE bus side.
> Some times the write value is written to the next address of it's
> destination.
> To test the phenominan I excuted the following code repeatedly.
>
> *(volatile unsigned int*)adrs = adrs; //Write value
> value = *(volatile unsigned int*)(adrs+4); // Read value of the next
> address
> if (value == (unsigned int)addr) // If the value is same

as
> adrs print error message
> printf ("Error at %08lx : %08x\n", (unsigned long)(adrs+4),

value);
> > As you can see the error message should never be appeared. > But it is sometimes appeared when the PCI bus is busy. > Does anyone in this list had the problem? > > Regards, > Sangmoon Kim > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/pci
_______________________________________________ http://www.opencores.org/mailman/listinfo/pci



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