Hi,
Sorry for any inconvenience; I'm using the Opencores PCI bridge for an
Firewire application, with an Altera Apex FPGA and NIOS processor.I'm using
the the Host configuration of the bridge; before make proves with the PCI side
of the bridge, i'm attempt read the PCI configuration space header (00h to
3Ch), but have the following problem:

after read the fixe registers of this space i'm obtain the values (Device,
vendor,...) in a mess!!

somewane has a similar problems? can help me?
Thanks and sorry to disturb you.

jose maria illa