I'm working on a device that will do almost exclusively scatter- gather reads through the PCI core. I want the board to read video, so it really most do burst reads. I'm targetting a Xilinx Virtex-II. I'm connecting a Wishbone master point-to-point to the PCI Wishbone slave interface, my host driver is setting the cache line size, and the Wishbone device is driving CTI to indicate bursts. But in my simulation traces the wb_pci core is only generating single-word reads. I need bursts. It's gonna read megabytes of video data! I see from rumma ging in the source that the wb image needs to be marked as prefetchable, but I see no efine or parameter that I can set to make it so. So given I defined NO_CNF_IMAGE, how to I enable prefetching and memory-read-line? The most obviously significat settings that I define: efine GUEST efine NO_CNF_IMAGE /* ADDR_TRAN_IMPL not defined */ -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

hi:
The Burst read and memory read line are not defined in the pci_user_constants.v
Before you used the CPU-PCI Bridge, you must configure the registers in the Bridge by Wishbone Interface to write proper data to them. (pls see "PCI IP Core Specification pp 35 for reference".
the Bit 0~1 in W_IMG_CTRLx (x=1..5) control the Image read transaction: (pls see "PCI IP Core Specification pp39)
if PREF_EN and MRL_EN:
00 (default): No burst read, all burst read from wishbone will be divided into single read;
10 : Memory Burst Read Enable;
01 : Memory Read Line Enable;
11 : Memory Read Multiple Enable.
You should configure it to the proper value before use each Image.

Syang wrote:
Darn, so there is no way to preconfigure this setup at compile time? The thing is, I have no CPU on the WB side of the device, so if I can't compile in this behavior, I am going to have to write a state machine to configure the core and then get out of the way? I even defined the NO_CNF_IMAGE directive because I hoped I could get away with not using the configuration space for anything. I really want all 32bits of address to pass directly through to the PCI side. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ http://www.opencores.org/mailman/listinfo/pci