Hello,
After synthesing the oc pci core (configuration identical to the crt
application) with webpack 6.2 (XST), I generated the post-synthesis
simulation model (using ngd2vhdl). But the resulting simulation model
did not answer properly to my testbench: the core does not even
accepts pci configuration accesses.
Is there a known problem with this version of the webpack ? How should
I proceed for a successfull synthesis ?

Thanks,
Brice