Hi,

I'm trying to use the PCI 2 WB bridge in an ALTERA Cyclone FPGA, and I'm looking for informations about changing the Xilinx RAMB4_S16_S16 RAM Blocks into Altera M4KRAM using Altera's macro : altsyncram.
The FPGA is successfully enumerated by the host CPU, but when I try to access to the WB bus through the FIFOs, I only get zeros "0x00000000", despite the fact that implemented a simple 32bits register as a WB slave (initializeed with a value different than "0x00000000").

Thanks for help.

F. A.

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