Greetings to all, My name is George Michelogiannakis and i am an undergraduate student studying at the university of crete and working at the research institute of Heraklion-Crete (http://www.ite.gr/). As my degree project and in cooperation with the research institute, we plan to use the PCI Wishbone bridge module to convert it to a PCI bridge for another bus. For this reason, we now want to make the PCI Wishbone module run under simulation using the nclaunch utilities. I've read the documentation and located the .scr script for this purpose, but it produces errors. Specifically, after it compiles all the source files it produces the following output: @@@ @@@ Building design hierarchy (elaboration) @@@ ncelab: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc. Elaborating the design hierarchy: Caching library 'worklib' ....... Done Caching library 'std' ....... Done Caching library 'synopsys' ....... Done Caching library 'ieee' ....... Done Caching library 'ambit' ....... Done Caching library 'vital_memory' ....... Done Caching library 'ncutils' ....... Done Caching library 'cds_assertions' ....... Done Caching library 'sdilib' ....... Done ncelab: *E,CUVMUR: instance of module/UDP 'RAMB4_S16_S16' is unresolved in 'worklib.pci_wb_tpram:module'. ncelab: *E,CUVMUR: instance of module/UDP 'pci_ram_16x40d' is unresolved in 'worklib.pci_pci_tpram:module'. ### ### Running tests (this takes a long time) ### ncsim: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc. ncsim: *F,NOSNAP: snapshot 'worklib.bridge32:fun' does not exist in the libraries. TESTS couldn't start due to Errors! I would be grateful for any suggestions or solutions for this problem. I have compiled and ran some testbenches on their own and most compile with no problem. Thank you in advance, George Michelogiannakis _______________________________________________ http://www.opencores.org/mailman/listinfo/pci