Greetings to everyone,
After studying a bit how the project (including the testbench) works,
i would like to ask you these questions just to make sure i am on the
right track.

1). I am trying to see if the project can use a 64 bit pci bus safely. My
question is if simply commenting in the PCI_BUS_SIZE_64 constant located
in pci_blue_options.vh will take care of all the side effects such as
increasing the fifo width, all the registers storing data or address in
all modules, etc. I am worried because this variable is not explained in
the documentation (i may have missed it) but mostly because i have seen
elements of the testbench located in system.v which are 32 bit constantly,
and do not use any define variables. One example for this is:
reg [31:0] wmem_data [0:1023] ; // data for memory mapped image writes
reg [31:0] wio_data [0:1023] ; // data for IO mapped image writes
(line 776 at system.v) but mostly the fact that the behavioral target
divices base addresses are defined as 32 bit address values in
pci_testbench_defines.v.
So, can i simply define this constant and have a 64 bit bus module and
testbench, or there are problems to fix?

2). My second goal is to use the testbench to simulate a pci bus without
the pci bridge, or at least without using the bridge. After studying the
system.v file i have an idea on how the simulation works. The two pci
behavioral devices can be set to act as master and target and execute
certain commands so my guess is that if i change the tests to instruct one
pci device to act as master and talk to another pci target (not the
bridge) for a certain transaction.All i am looking for is things to watch
out for and a confirmation that removing the bridge is doable so i can
have the pci bus remaining.

Thank you all in advance and good luck with your projects,
George Michelogiannakis