Sorry for this second mail

After editing the system.v file located in bench/verilog and removing many
tasks, it no longer produces a cds.lib file which i can use. I was
wondering if you have any idea which part of the project is responsible
for creating and saving the data into the cds.lib file located at
sim/rtl_sim/bin so i can use it then in nclaunch.

I have only left the configure_target and do_reset tasks running, and call
PCIU_MEM_READ and PCIU_MEM_WRITE myself seperately so as to have a PCI bus
without the bridge and wishbone bus. Is there a way i can have a proper
cds.lib file for only the PCI bus transactions?

Thank you,
Mihelogiannakis Giorgos