I have used the PCI core in a project. I have attached some simple registers to the wishbone master bus. When I read the registers via the PCI bus the data seems to be cached in the PCI core. For example:- First read I get the contents of the registers. Second read (I am polling a register waiting for status change) I get the same values, but meanwhile register contents have changed (did I even get a wishbone master read?). If I read a different register, then re-read the register I get new contents. Has anyone else seen the same behaviour, is there a work round other than do dummy reads from different addresses to flush the PCI core fifo's? Regards Dave Warren dave@luscher.co.uk