Greetings to everyone,
I have a few questions on the testbench of the PCI Bridge project as
well as the project itself. Thank you in advance for your time. These
questions have been posted before and i must say i haven't worked on them
really because of the Olympic games but now the show must go on!

1).I am trying to see if the project can use a 64 bit pci bus safely. My
question is if simply commenting in the PCI_BUS_SIZE_64 constant located
in pci_blue_options.vh will take care of all the side effects such as
increasing the fifo width, all the registers storing data or address in
all modules, etc. I am worried because this variable is not explained in
the documentation (i may have missed it) but mostly because i have seen
elements of the testbench located in system.v which are 32 bit constantly,
and do not use any define variables. One example for this is:
reg [31:0] wmem_data [0:1023] ; // data for memory mapped image writes
reg [31:0] wio_data [0:1023] ; // data for IO mapped image writes
(line 776 at system.v) but mostly the fact that the behavioral target
divices base addresses are defined as 32 bit address values in
pci_testbench_defines.v.
So, can i simply define this constant and have a 64 bit bus module and
testbench, or there are problems to fix?

2). After editing the system.v file located in bench/verilog and removing
many
tasks, it no longer produces a cds.lib file which i can use. I was
wondering if you have any idea which part of the project is responsible
for creating and saving the data into the cds.lib file located at
sim/rtl_sim/bin so i can use it then in nclaunch.

I have only left the configure_target and do_reset tasks running, and call
PCIU_MEM_READ and PCIU_MEM_WRITE myself seperately so as to have a PCI bus
without the bridge and wishbone bus. Is there a way i can have a proper
cds.lib file for only the PCI bus transactions?

The cds.lib it does produce does not contain any waveforms inside it when
i open it with ncview. The simulation however does seem to run since if i
put a $display inside the code it does display it. Also, the PCI bus
does exist, but it does not have the PCI Bridge and Wishbone bus parts.

3). I am using the PCIU_MEM_READ and PCIU_MEM_WRITE tasks to instruct a
pci behavioral device instance to do something i want to be done in the
PCI bus. My goal is to create a simulation of a PCI bus with devices
performing various tasks. However, when i instruct a device to act as
master and to read from a target's memory, i have no way of receiving the
data from the task, but only providing the data i expect to read. I have
located an output (PCI_BUS_DATA_RANGE bits long) of the
pci_behavrioal_device module named master_received_data but even after
calling these tasks to perform an action, this output remains X. This can
either mean that nothing actually ever runs (in conjuction with the
cds.lib file problem) or that this output is not what i think it is.

Any opinions are very welcome. Thank you in advance,
George Michelogiannakis