An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/pci/attachments/20040831/81a83e6b/attachment.htm -------------- next part --------------  Hi There, I would like to know that what should be the actual value of the AD lines during the configuration read transaction of the command and status registers. The following gives an idea for the reason for my confussion. 1. The specs says that you can access any 1 of the 64 DWORDS present in the configuration space. 2. You have 6 bits to do that, bits AD[7:2] to do that. 3. Some user manuals have the PCI offset address of the command and status registers DWORD as 04H. 4. Now if you use 04H (000100B)as the actual address on the AD lines for accessing the command and status registers you can actually only the first 16 DWORD registers of the configuration space. 5. My observation is that you will have to use 01H (000001B) to access command and status registers and not 04H 6. Why have the user guides have mentioned 04H and not 01H will be awaiting for your reply and thanks. AMITH KUMAR .G