I have successfully implemented the PCI core in an Altera Cyclone EP1C12Q240C8 device. It is used as a PCI target only (the wishbone slave interface is just tied off and the logic compiler removes unused logic), on an embedded processor board. Generally it works well. However I get some SERR which causes the system to crash. It seems to be timing related, if I change the logic in any way and recompile, I use Quartus II web, then there is a chance that the result will be stable and not show any SERR's, or it will show SERR's after 10 minutes of heavy PCI bus activity. I can capture the SERR event using the Quartus Signaltap logic analyer, and it seems there is nothing wrong with Parity so the timing fault must be in the parity checker. Also after SERR the PCI core stops responding to PCI bus cycles, the next PCI FRAME with a good address is not followed by a DEVSEL. Is this expected? Any feedback would be a help, has anyone used the core in Cyclone? I can post the changes I made to implement the core in Altera if it would help anyone. Dave Warren dave@luscher.co.uk

Hi! This really sounds like a timing problem. If you have a lot of boards on your PCI Bus, try removing them one by one and see if that helps. If it does, then it is timing for sure. Could you send me your constraints file and implementation log file? I'm not familiar with Altera nor Quartus but would like to check if I can find out something anyway. Where did you get the board - did you buy it or made it yourself? Please don't send the files to the mailing list - some people don't like that. Regards, Miha Dolenc ----- Original Message ----- From: "Dave Warren" dave@luscher.co.uk> To: pci@opencores.org> Sent: Thursday, September 16, 2004 11:16 AM Subject: [pci] SERR due to timing in Altera Cyclone
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Dave Warren a écrit :


Yes, we're using a EP1C12 with the PCI core. We've not yet encountered a
problem. We've implements the core with master and slave unit in order
to realize DMA transfer.

-- Laurent

Hi Laurent, Could you please send me copys of files you needed to edit to get the PCI core to work in a EP1C12? Send files direct not on the discussion list. Also it would be helpfull it you coulod let me know what assignments you made to PCI pins ect in the device regards Dave ----- Original Message ----- From: "Laurent" lbroto@free.fr> To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Sent: Thursday, September 16, 2004 5:11 PM Subject: Re: [pci] SERR due to timing in Altera Cyclone Dave Warren a écrit : Yes, we're using a EP1C12 with the PCI core. We've not yet encountered a problem. We've implements the core with master and slave unit in order to realize DMA transfer. -- Laurent _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

Dave Warren a écrit :


Hi Dave !

We didn't modify any file. We just create a new component named
ramb4_s16_s16 which use M4K block to emulate ramb4_s16_s16. If you want
I can send you this file.


What kind of assignement do you want ? Pins ? Timing ? IO Level ? If you
want I can send you a copy of my Assigment Editor (monday only, today
I'm not at my office). However, we've created a board with the FPGA. So
assigment are specific to our board.

Regards,

-- Laurent

Hi Dave and Laurent,
I'm also trying to implement the PCI opencore in an Altera Cyclone EP1C4F400 (using QuartusII free web edition). I replaced the Xilinx's type RAM Blocks (ramb4_s16_s16) by Altera's M4K RAM, but I face problem with the wishbone bus : the SEL line does not behave as described in the WishBone specification. May be my M4K RAM use is not correct. Could you also send me your file ?
Thank you.
Frederic.



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