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An update on SERR problems
by Unknown on Oct 29, 2004 |
Not available! | ||
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My SERR problems never went away they just got very rare. The update from
Miha did not help.
However I think I have found a bug in the OPENCORE PCI. SERR is disabled
because control register bit 8 is zero. So a SERR internally should not be
driven out, but the SERR should set bit 14 in the status register. But if a
SERR then PCI target does not terminate the PCI bus cycle, DEVSEL is removed
but there is no TRDY or STOP, (also no external SERR because of bit 8). This
upsets my PCI master and nothing happens after that.
I have not fixed it but as a work around I have disabled the internal SERR
so the status bit is no longer set. File pci_parity_check.v like this.
// SERR# output is always 0, just enable is driven apropriately
pci_serr_crit serr_crit_gen
(
.serr_out (pci_serr_out),
.non_critical_par_in (non_critical_par),
.pci_par_in (pci_par_in),
.serr_check_in (serr_generate) //(check_for_serr)
);
Now at least the system does not lock.
Dave Warren
dave@luscher.co.uk
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An update on SERR problems
by Unknown on Nov 2, 2004 |
Not available! | ||
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Hi!
As I remember, we already determined that your implementation looks OK.
(You sent me the synthesis logs?)
Did you try plugging some other PCI board into the same slot and access it?
Does it work? What I'm wondering is - could there be a problem with the
system or add-in board?
Regards,
Miha Dolenc
----- Original Message -----
From: "Dave Warren" dave@luscher.co.uk>
To: pci@opencores.org>
Sent: Friday, October 29, 2004 5:25 PM
Subject: [pci] An update on SERR problems
My SERR problems never went away they just got very rare. The update from Miha did not help. However I think I have found a bug in the OPENCORE PCI. SERR is disabled because control register bit 8 is zero. So a SERR internally should not be driven out, but the SERR should set bit 14 in the status register. But if a
SERR then PCI target does not terminate the PCI bus cycle, DEVSEL is
removed
but there is no TRDY or STOP, (also no external SERR because of bit 8).
This
upsets my PCI master and nothing happens after that.
I have not fixed it but as a work around I have disabled the internal SERR
so the status bit is no longer set. File pci_parity_check.v like this.
// SERR# output is always 0, just enable is driven apropriately
pci_serr_crit serr_crit_gen
(
.serr_out (pci_serr_out),
.non_critical_par_in (non_critical_par),
.pci_par_in (pci_par_in),
.serr_check_in (serr_generate) //(check_for_serr)
);
Now at least the system does not lock.
Dave Warren
dave@luscher.co.uk
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
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