Just to update everyone. It seems the SERR errors are due to noise on the PCB or in the power supply. Changing the logic options for all outputs to SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone devices need a very good PCB and large amounts of decoupling for the power. I will modify the PCB layout and make some more to see if I can improve the PCB so I no longer get errors. Thanks to all who replied. Dave Warren dave@luscher.co.uk _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

Just to update everyone. It seems the SERR errors are due to noise on the PCB or in the power supply. Changing the logic options for all outputs to SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone devices need a very good PCB and large amounts of decoupling for the power. I will modify the PCB layout and make some more to see if I can improve the PCB so I no longer get errors. Thanks to all who replied. Dave Warren dave@luscher.co.uk _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

Just to update everyone. It seems the SERR errors are due to noise on the PCB or in the power supply. Changing the logic options for all outputs to SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone devices need a very good PCB and large amounts of decoupling for the power. I will modify the PCB layout and make some more to see if I can improve the PCB so I no longer get errors. Thanks to all who replied. Dave Warren dave@luscher.co.uk _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

You wont need a cap for each power pin. That is a conservative estimate, and just that an estimate. On BGA designs its not even practical. Since however you are working with a PQ package, it might be possible. Just use a handfull, say 10, .1uF ceramic X7R caps at or near the power pins. Space the caps evenly around the package. Then near the voltage regulator place a 1uF or a 10uF ceramic or tantalum capacitor, whichever is cheaper. Do this for all the power rails you are using. Using a solid power plane and a solid ground plane on layers 2 and 3 on a 4 layer board, will also help with the power decoupling. Testing: Run your design at maximum rate and load. Place a scope probe with a short lead on a power pin, and AC couple the scope. Use the scope to see what frequencies are present on the DC power line. Ideally there shouldn't be any. Keep the ripple voltage below the maximum and above minimum rated voltages for the Xilinx. If you have signifigant ripple, add more caps until things even out. You'll need a mixure of bulk and high frequency caps to do the job. You won't need more than 22uF-40uF bulk capacitence per rail. You'll need 1 .1uF capacitor per 1 to 3 power pins. Do not use .01uF for your design. -----Original Message----- From: pci-bounces@opencores.org [mailto:pci-bounces@opencores.org]On Behalf Of Rohit Mathur Sent: Tuesday, November 09, 2004 9:34 PM To: Discussion list about free,open source PCI IP core Subject: Re: [pci] SERR due to board layout errors ? [another capacitor Q] Hi Cristian, I am not really sure about Xilinx, but even then in general, decoupling caps should be placed at each power pin. And since youre talking about the 2.5V core voltage, you can reasonably be sure of errors once you utilize close to the logic capacity of the device. Just one decap at the voltage regulator might not be enough. Regards Rohit ----- Original Message ----- From: "Balint Cristian" rezso@rdsor.ro> To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Sent: 09 November 2004 16:55 Subject: Re: [pci] SERR due to board layout errors ? [another capacitor Q] On Monday 08 November 2004 14:50, Dave Warren wrote:

Hi guys,

Want to ask that i designed a board and in a gread wisdom of mine to save
space i left out capacitors near
2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage
regulator [at 5 cm from xilinx] but not
in cloase near of each input of 2.5 line of xilinx as I see that is
practiced in more designs.

I plan to use the board ar 33Mhz, does my mistake affect something in
functionality ?

I am a little bit desperate :), hope not to throw out the design. can I
ask
your opinnion ?

What method to apply in measuring if its ok or not ? Osciloscope ?
Is there a PCI test tool [windows] or something to test throughoutput and
the reliability of core/board
to see in time the resistance over speed stress ?

Thanks in advance,
~cristian


_______________________________________________ http://www.opencores.org/mailman/listinfo/pci _______________________________________________ http://www.opencores.org/mailman/listinfo/pci _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

Message du 09/11/04 à 12h36
De : "Balint Cristian"
A : "Discussion list about free, open source PCI IP core"
Copie à :
Objet : Re: [pci] SERR due to board layout errors ? [another capacitor Q]
On Monday 08 November 2004 14:50, Dave Warren wrote:


Hi guys,

Want to ask that i designed a board and in a gread wisdom of mine to save space i left out capacitors near
2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage regulator [at 5 cm from xilinx] but not
in cloase near of each input of 2.5 line of xilinx as I see that is practiced in more designs.

I plan to use the board ar 33Mhz, does my mistake affect something in functionality ?

I am a little bit desperate :), hope not to throw out the design. can I ask your opinnion ?

What method to apply in measuring if its ok or not ? Osciloscope ?
Is there a PCI test tool [windows] or something to test throughoutput and the reliability of core/board
to see in time the resistance over speed stress ?

Thanks in advance,
~cristian


_______________________________________________ http://www.opencores.org/mailman/listinfo/pci