Hi, Friends, Is it easy to compile pci_bridge32 on cyclone with c7 speed and meet 66Mhz pci requirement? I try to compile the pci+crt on quartus41 web edition, without pin assignment, with Tsu constraint to 3ns and Tco to 7ns. The result is that the design takes 2624 LEs and 13168 memory bits. The worst case Tsu is 4.9 ns. All critical signals like irdy, trdy, frame, stop dont meet the timing requirement :( Will it be better after pin assignment? The device is EP1C6Q240C7 Regards --------------------------------- Do you Yahoo!? Check out the new Yahoo! Front Page. www.yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/pci/attachments/20041111/3abdb968/attachment.htm