1/1 
|
PCI ?
by Unknown on Nov 17, 2004 |
Not available! | ||
|
Hi Everyone
A General information required,the present pentium 4 systems are compatible with PCI Express slots ? Thanks & Regards Velu.V |
|||
|
PCI ?
by Unknown on Nov 26, 2004 |
Not available! | ||
|
Hi PCI Team
Kindly let me know clear definition and description of
"Reflected wave Switching" in PCI 2.2 or PC 2.3
Thanks & Regards
Velu.V
On Fri, 19 Nov 2004 13:02:06 +0100, pci-request@opencores.org
pci-request@opencores.org> wrote:
Send Pci mailing list submissions to
pci@opencores.org
To subscribe or unsubscribe via the World Wide Web, visit
http://www.opencores.org/mailman/listinfo/pci
or, via email, send a message with subject or body 'help' to
pci-request@opencores.org
You can reach the person managing the list at
pci-owner@opencores.org
When replying, please edit your Subject line so it is more specific
than "Re: Contents of Pci digest..."
Today's Topics:
1. Re: SERR due to board layout errors ? [another capacitor Q]
(Rohit Mathur)
2. RE: SERR due to board layout errors ? [another capacitor Q]
(DANIEL BYRNE)
3. Re: SERR due to board layout errors ? [another capacitor Q]
(Balint Cristian)
4. pci on cyclone c7 (rat nothis)
5. Re: Re: [pci] SERR due to board layout errors ? [another
capacitor Q] (Frederic AUTRET)
6. PCI ? (Velayutham Venkatachalapathy)
7. I want to test it (Zeng Bo)
8. VHDL code for PCI Interface (dmhung1c@yahoo.com)
9. VHDL code for PCI Interface (dmhung1c@yahoo.com)
10. reg. wait states in PCI (vijaykumar_gampa@yahoo.com)
----------------------------------------------------------------------
Message: 1
Date: Wed, 10 Nov 2004 09:03:37 +0530
From: "Rohit Mathur" rohitmathurs@hotmail.com>
Subject: Re: [pci] SERR due to board layout errors ? [another
capacitor Q]
To: "Discussion list about free,open source PCI IP core"
pci@opencores.org>
Message-ID: BAY15-DAV13LTkUD5eu0001fa07@hotmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi Cristian,
I am not really sure about Xilinx, but even then in general, decoupling caps
should be placed at each power pin. And since youre talking about the 2.5V
core voltage, you can reasonably be sure of errors once you utilize close to
the logic capacity of the device.
Just one decap at the voltage regulator might not be enough.
Regards
Rohit
----- Original Message -----
From: "Balint Cristian" rezso@rdsor.ro>
To: "Discussion list about free, open source PCI IP core"
pci@opencores.org>
Sent: 09 November 2004 16:55
Subject: Re: [pci] SERR due to board layout errors ? [another capacitor Q]
On Monday 08 November 2004 14:50, Dave Warren wrote:
>
Hi guys, Want to ask that i designed a board and in a gread wisdom of mine to save space i left out capacitors near 2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage regulator [at 5 cm from xilinx] but not in cloase near of each input of 2.5 line of xilinx as I see that is practiced in more designs. I plan to use the board ar 33Mhz, does my mistake affect something in functionality ? I am a little bit desperate :), hope not to throw out the design. can I ask your opinnion ? What method to apply in measuring if its ok or not ? Osciloscope ? Is there a PCI test tool [windows] or something to test throughoutput and the reliability of core/board to see in time the resistance over speed stress ? Thanks in advance, ~cristian
> Just to update everyone. It seems the SERR errors are due to noise on the
> PCB or in the power supply. Changing the logic options for all outputs to
> SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone
> devices
> need a very good PCB and large amounts of decoupling for the power. I will
> modify the PCB layout and make some more to see if I can improve the PCB
> so
> I no longer get errors. Thanks to all who replied.
>
> Dave Warren
>
> dave@luscher.co.uk
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
------------------------------
Message: 2
Date: Wed, 10 Nov 2004 09:49:43 -0600
From: DANIEL BYRNE daniel.byrne@adtran.com>
Subject: RE: [pci] SERR due to board layout errors ? [another
capacitor Q]
To: "'Discussion list about free, open source PCI IP core'"
pci@opencores.org>
Message-ID:
39B01E2189D99F4B8C9612462DB3922A153B95B6@srv-exchange.adtran.com>
Content-Type: text/plain; charset="iso-8859-1"
You wont need a cap for each power pin. That is a conservative estimate, and just that an estimate. On BGA designs its not even practical. Since however you are working with a PQ package, it might be possible. Just use a handfull, say 10, .1uF ceramic X7R caps at or near the power pins. Space the caps evenly around the package. Then near the voltage regulator place a 1uF or a 10uF ceramic or tantalum capacitor, whichever is cheaper. Do this for all the power rails you are using. Using a solid power plane and a solid ground plane on layers 2 and 3 on a 4 layer board, will also help with the power decoupling.
Testing:
Run your design at maximum rate and load.
Place a scope probe with a short lead on a power pin, and AC couple the scope. Use the scope to see what frequencies are present on the DC power line. Ideally there shouldn't be any. Keep the ripple voltage below the maximum and above minimum rated voltages for the Xilinx. If you have signifigant ripple, add more caps until things even out. You'll need a mixure of bulk and high frequency caps to do the job. You won't need more than 22uF-40uF bulk capacitence per rail. You'll need 1 .1uF capacitor per 1 to 3 power pins. Do not use .01uF for your design.
-----Original Message-----
From: pci-bounces@opencores.org [mailto:pci-bounces@opencores.org]On
Behalf Of Rohit Mathur
Sent: Tuesday, November 09, 2004 9:34 PM
To: Discussion list about free,open source PCI IP core
Subject: Re: [pci] SERR due to board layout errors ? [another capacitor
Q]
Hi Cristian,
I am not really sure about Xilinx, but even then in general, decoupling caps
should be placed at each power pin. And since youre talking about the 2.5V
core voltage, you can reasonably be sure of errors once you utilize close to
the logic capacity of the device.
Just one decap at the voltage regulator might not be enough.
Regards
Rohit
----- Original Message -----
From: "Balint Cristian" rezso@rdsor.ro>
To: "Discussion list about free, open source PCI IP core"
pci@opencores.org>
Sent: 09 November 2004 16:55
Subject: Re: [pci] SERR due to board layout errors ? [another capacitor Q]
On Monday 08 November 2004 14:50, Dave Warren wrote:
>
Hi guys, Want to ask that i designed a board and in a gread wisdom of mine to save space i left out capacitors near 2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage regulator [at 5 cm from xilinx] but not in cloase near of each input of 2.5 line of xilinx as I see that is practiced in more designs. I plan to use the board ar 33Mhz, does my mistake affect something in functionality ? I am a little bit desperate :), hope not to throw out the design. can I ask your opinnion ? What method to apply in measuring if its ok or not ? Osciloscope ? Is there a PCI test tool [windows] or something to test throughoutput and the reliability of core/board to see in time the resistance over speed stress ? Thanks in advance, ~cristian
> Just to update everyone. It seems the SERR errors are due to noise on the
> PCB or in the power supply. Changing the logic options for all outputs to
> SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone
> devices
> need a very good PCB and large amounts of decoupling for the power. I will
> modify the PCB layout and make some more to see if I can improve the PCB
> so
> I no longer get errors. Thanks to all who replied.
>
> Dave Warren
>
> dave@luscher.co.uk
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
------------------------------
Message: 3
Date: Thu, 11 Nov 2004 20:32:53 +0200
From: "Balint Cristian" rezso@rdsor.ro>
Subject: Re: [pci] SERR due to board layout errors ? [another
capacitor Q]
To: "Discussion list about free, open source PCI IP core"
pci@opencores.org>
Message-ID: fdbce7c1@yoda>
Content-Type: text/plain; format=flowed; charset="iso-8859-1";
reply-type=original
Thank you Daniel !
You really gived me a strong advice. I will do the tests.
----- Original Message -----
From: "DANIEL BYRNE" daniel.byrne@adtran.com>
To: "'Discussion list about free, open source PCI IP core'"
pci@opencores.org>
Sent: Wednesday, November 10, 2004 5:49 PM
Subject: RE: [pci] SERR due to board layout errors ? [another capacitor Q]
> You wont need a cap for each power pin. That is a conservative estimate,
> and just that an estimate. On BGA designs its not even practical. Since
> however you are working with a PQ package, it might be possible. Just use
> a handfull, say 10, .1uF ceramic X7R caps at or near the power pins.
> Space the caps evenly around the package. Then near the voltage regulator
> place a 1uF or a 10uF ceramic or tantalum capacitor, whichever is cheaper.
> Do this for all the power rails you are using. Using a solid power plane
> and a solid ground plane on layers 2 and 3 on a 4 layer board, will also
> help with the power decoupling.
>
> Testing:
> Run your design at maximum rate and load.
> Place a scope probe with a short lead on a power pin, and AC couple the
> scope. Use the scope to see what frequencies are present on the DC power
> line. Ideally there shouldn't be any. Keep the ripple voltage below the
> maximum and above minimum rated voltages for the Xilinx. If you have
> signifigant ripple, add more caps until things even out. You'll need a
> mixure of bulk and high frequency caps to do the job. You won't need more
> than 22uF-40uF bulk capacitence per rail. You'll need 1 .1uF capacitor
> per 1 to 3 power pins. Do not use .01uF for your design.
>
> -----Original Message-----
> From: pci-bounces@opencores.org [mailto:pci-bounces@opencores.org]On
> Behalf Of Rohit Mathur
> Sent: Tuesday, November 09, 2004 9:34 PM
> To: Discussion list about free,open source PCI IP core
> Subject: Re: [pci] SERR due to board layout errors ? [another capacitor
> Q]
>
>
> Hi Cristian,
>
> I am not really sure about Xilinx, but even then in general, decoupling
> caps
> should be placed at each power pin. And since youre talking about the 2.5V
> core voltage, you can reasonably be sure of errors once you utilize close
> to
> the logic capacity of the device.
> Just one decap at the voltage regulator might not be enough.
>
> Regards
>
> Rohit
> ----- Original Message -----
> From: "Balint Cristian" rezso@rdsor.ro>
> To: "Discussion list about free, open source PCI IP core"
> pci@opencores.org>
> Sent: 09 November 2004 16:55
> Subject: Re: [pci] SERR due to board layout errors ? [another capacitor Q]
>
>
> On Monday 08 November 2004 14:50, Dave Warren wrote:
------------------------------
Message: 4
Date: Thu, 11 Nov 2004 18:44:57 -0800 (PST)
From: rat nothis nothisrat@yahoo.com>
Subject: [pci] pci on cyclone c7
To: pci@opencores.org
Message-ID: 20041112024457.10678.qmail@web50002.mail.yahoo.com>
Content-Type: text/plain; charset="us-ascii"
Hi, Friends,
Is it easy to compile pci_bridge32 on cyclone with c7 speed and meet 66Mhz pci requirement? I try to compile the pci+crt on quartus41 web edition, without pin assignment, with Tsu constraint to 3ns and Tco to 7ns. The result is that the design takes 2624 LEs and 13168 memory bits. The worst case Tsu is 4.9 ns. All critical signals like irdy, trdy, frame, stop dont meet the timing requirement :( Will it be better after pin assignment? The device is EP1C6Q240C7
Regards
---------------------------------
Do you Yahoo!?
Check out the new Yahoo! Front Page. www.yahoo.com
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://www.opencores.org/forums/pci/attachments/20041111/3abdb968/attachment-0001.htm
------------------------------
Message: 5
Date: Tue, 16 Nov 2004 09:34:29 +0100 (CET)
From: Frederic AUTRET autretfr@voila.fr>
Subject: Re: Re: [pci] SERR due to board layout errors ? [another
capacitor Q]
To: Discussion list about free open source PCI IP core
pci@opencores.org>
Message-ID: 10928697.1100594069087.JavaMail.www@wwinf4103>
Content-Type: text/plain; charset=iso-8859-1
Hi Cristian,
There is a Xilinx Application Note about bypass and decoupling capacitors : XAPP623 that you can download on the Xilinx web site.
Fred.
>
> > Hi guys, > > Want to ask that i designed a board and in a gread wisdom of mine to save > space i left out capacitors near > 2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage > regulator [at 5 cm from xilinx] but not > in cloase near of each input of 2.5 line of xilinx as I see that is > practiced in more designs. > > I plan to use the board ar 33Mhz, does my mistake affect something in > functionality ? > > I am a little bit desperate :), hope not to throw out the design. can I > ask > your opinnion ? > > What method to apply in measuring if its ok or not ? Osciloscope ? > Is there a PCI test tool [windows] or something to test throughoutput and > the reliability of core/board > to see in time the resistance over speed stress ? > > Thanks in advance, > ~cristian > >
> Just to update everyone. It seems the SERR errors are due to noise on the
> PCB or in the power supply. Changing the logic options for all outputs to
> SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone
> devices
> need a very good PCB and large amounts of decoupling for the power. I
> will
> modify the PCB layout and make some more to see if I can improve the PCB
> so
> I no longer get errors. Thanks to all who replied.
>
> Dave Warren
>
> dave@luscher.co.uk
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
> Message du 09/11/04 Ã 12h36
------------------------------------------
Faites un voeu et puis Voila ! www.voila.fr
------------------------------
Message: 6
Date: Wed, 17 Nov 2004 08:53:08 +0530
From: Velayutham Venkatachalapathy velu27@gmail.com>
Subject: [pci] PCI ?
To: pci@opencores.org
Message-ID: ef4b9a6e0411161923a32efe1@mail.gmail.com>
Content-Type: text/plain; charset=US-ASCII
Hi Everyone
A General information required,the present pentium 4 systems are
compatible with PCI Express slots ?
Thanks & Regards
Velu.V
------------------------------
Message: 7
Date: Sun, 24 Oct 2004 11:00:47 +0800
From: Zeng Bo zeng79@gmail.com>
Subject: [pci] I want to test it
To: pci@opencores.org
Message-ID: 7e65ea7704102320001845f782@mail.gmail.com>
Content-Type: text/plain; charset=US-ASCII
I am an IC designer, I want join some project such as PCI, but the
project of PCI bridge has been done. So I want to help to test it.
If you have some new project to create, please inform me to join it. thanks.
PS: How can I get an opencores account to create my own porject? Thanks again.
--
Zeng bo
Chengdu , China
------------------------------
Message: 8
Date: Wed, 27 Oct 2004 09:45:28 +0200
From: dmhung1c@yahoo.com
Subject: [pci] VHDL code for PCI Interface
To: pci@opencores.org
Message-ID: 200410270745.i9R7jSpv015599@www.opencores.org>
Hi all ! ! !
I am learning to make a PCI Interface controller chip using CPLD.
so I must Write a VHDL code. What must I do to write VHDL code for
PCI interface???? Who can help me?????
------------------------------
Message: 9
Date: Wed, 27 Oct 2004 09:51:31 +0200
From: dmhung1c@yahoo.com
Subject: [pci] VHDL code for PCI Interface
To: pci@opencores.org
Message-ID: 200410270751.i9R7pVC2016542@www.opencores.org>
Hi ! ! !
I am learning to make a PCI target interface chip using
CPLD. so I must write VHDL code for it. What must I do???? Who can
help me????
Thank ........
Please contact me dmhung1c@yahoo.com if possible
------------------------------
Message: 10
Date: Fri, 19 Nov 2004 05:29:41 +0100
From: vijaykumar_gampa@yahoo.com
Subject: [pci] reg. wait states in PCI
To: pci@opencores.org
Message-ID: 200411190429.iAJ4TfBG032312@www.opencores.org>
1.what are the maximum no. of wiat states that can be inserted in
PCI,AHB and VCI.
2.whether arbiter will check the transaction is going r not?
if yes , what r maximum no. of cycles that the bus may be in idle in
case of PCI and VCI and AHB.
plz reply to
VIjaykumar_gampa@yahoo.com
Thanks and Regards,
vijay
------------------------------
_______________________________________________
Pci mailing list
Pci@opencores.org
http://www.opencores.org/mailman/listinfo/pci
End of Pci Digest, Vol 11, Issue 2
**********************************
> De : "Balint Cristian" > A : "Discussion list about free, open source PCI IP core" > Copie à : > Objet : Re: [pci] SERR due to board layout errors ? [another capacitor Q] > On Monday 08 November 2004 14:50, Dave Warren wrote:
>
> > Hi guys, > > Want to ask that i designed a board and in a gread wisdom of mine to save space i left out capacitors near > 2.5V pins wich supply an XC2S200-Pq208, i have capacitor only at voltage regulator [at 5 cm from xilinx] but not > in cloase near of each input of 2.5 line of xilinx as I see that is practiced in more designs. > > I plan to use the board ar 33Mhz, does my mistake affect something in functionality ? > > I am a little bit desperate :), hope not to throw out the design. can I ask your opinnion ? > > What method to apply in measuring if its ok or not ? Osciloscope ? > Is there a PCI test tool [windows] or something to test throughoutput and the reliability of core/board > to see in time the resistance over speed stress ? > > Thanks in advance, > ~cristian > >
> Just to update everyone. It seems the SERR errors are due to noise on the
> PCB or in the power supply. Changing the logic options for all outputs to
> SLOW SLEW RATE reduced the chance of an error. Maybe Altera Cyclone devices
> need a very good PCB and large amounts of decoupling for the power. I will
> modify the PCB layout and make some more to see if I can improve the PCB so
> I no longer get errors. Thanks to all who replied.
>
> Dave Warren
>
> dave@luscher.co.uk
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/pci
>
|
|||
|
PCI ?
by Unknown on Dec 10, 2004 |
Not available! | ||
|
Yes they are compatible..
Regards
Sayed Zeeshan
----- Original Message -----
From: Velayutham Venkatachalapathyvelu27@g...>
To:
Date: Wed Nov 17 04:23:08 CET 2004
Subject: [pci] PCI ?
Hi Everyone
A General information required,the present pentium 4 systems are compatible with PCI Express slots ? Thanks & Regards Velu.V |
|||
1/1