Hi
1. My question is that Can PCI target do DMA transfers... or is it
confined only to PCI master....
2. If there is a burst mode support in target, is there any need to do
DMA transfers?

Targets can not initiate transfers. Only masters can.

DMA was mainly used in the old days of ISA/EISA bus where the CPU was the
master, and all devices were slaves. On those legacy bus, there were no way
for the processor to transfer multiple data fast. There was a line on the
CPU, used as a bus request. The DMA module requested control of the BUS,
and while the CPU granted access, the CPU just stayed idle.

Now, with PCI, any devices on the PCI bus can initiate requests (provided
they have master capability). The request from one device to another are
theorically transparent to other devices on the bus. So, any board could
access memory, while the CPU is concurently processing. Of course, you
can't have two transactions at the same time on the bus, but the idea is
that, appart from initial configuration, the devices desn't have to rely on
other devices on the bus.

PCI masters can perform burst transfers. PCI target can reply to burst
read/write requests. A target doesn't have to comply to the burst request,
if it doesn't support it, or can initiate aborts after transfering part of
the burst. The master can then re-start from where the target have aborted.

The thing to remember is that targets can not initiate requests on their own
over the PCI bus. So, if you wish to access memory, you need to have a
master. And if you do have a master, and you know where the memory is (ex,
memory location configured by the software or driver in CPU), then your
device can access the memory on it's own, without having to wait for
specific request from the main CPU. PCI video cards that used what's called
in the industry as 'shared memory' use this principle. Though, this of
course may slow down other devices on the bus, but still look transparent to
them.

Thank you very much delta trinity for reply. But the problem is that our target supports burst transfers, so how would one tranfser data to RAM directly in burst mode??? Is it the task of cpu or what? On Mon, 13 Dec 2004 17:56:24 -0500, delta trinity deltatrinity@hotmail.com> wrote:


--
Sayed Zeeshan Asghar

Motherboard chip sets do not support burst transfer to PCI targets (slaves). ****************************************************************** If you need burst transfer you have to implement PCI master. I hope someone can prove me wrong. Regards, Richard ----- Original Message ----- From: "Sayed Zeeshan" sayedzeeshan@gmail.com> To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Sent: Tuesday, December 14, 2004 12:06 AM Subject: Re: [pci] PCI DMA

Richard Sliwinski wrote: > Motherboard chip sets do not support burst transfer to PCI targets (slaves). > ****************************************************************** > If you need burst transfer you have to implement PCI master. > I hope someone can prove me wrong. > Regards, Anybody working on PCI devices or device drivers must have a good sense for all this. Without a working understanding, you are doomed to a confused failure. I hear good things about books published by MindShare Inc. http://www.mindshare.com/>. A PCI device can accept a burst as a target, or can initiate a burst as a master. Any device in a typical PCI bus can be a master at any given moment, it is up to the arbiter (part of the motherboard) to grant a device access to the bus. So when one says that a device is a "target", then one is saying that a device is a target of a "transaction" and there is another master accessing that target device. Every PCI device supports at least being a target. When one says a device is "target-only" then one is saying that the device is not able to initiate a transaction. Target-only devices are relatively uncommon these days. One might think of a video card, for example, as a target-only device (although even that is probably not always true.) It is most common for a PCI device (i.e. ethernet card) to be capable of bus mastering. Without that capability, there is no DMA to that card. For example, an ethernet card is the target of transactions when the host writes registers to configure a transfer of a block of data to the wire. Then when started it initiates reads from memory to get the data. I.e. it acts as a master. It directly accesses the memory buffer for itself. It does "DMA". So a "target-only" device cannot do DMA. Burst mode has nothing to do with it. If a device does burst reads (i.e. the *device* reads from the PCI) then it can do DMA, and how you set it up is described in the device documentation. > ----- Original Message ----- > From: "Sayed Zeeshan" sayedzeeshan@gmail.com> > To: "Discussion list about free, open source PCI IP core" > pci@opencores.org> > Sent: Tuesday, December 14, 2004 12:06 AM > Subject: Re: [pci] PCI DMA > > > >>Thank you very much delta trinity for reply. >>But the problem is that our target supports burst transfers, so how >>would one tranfser data to RAM directly in burst mode??? >>Is it the task of cpu or what? >> >> >>On Mon, 13 Dec 2004 17:56:24 -0500, delta trinity >>deltatrinity@hotmail.com> wrote: >> >>>Targets can not initiate transfers. Only masters can. >>> >>>DMA was mainly used in the old days of ISA/EISA bus where the CPU was > > the > >>>master, and all devices were slaves. On those legacy bus, there were no > > way > >>>for the processor to transfer multiple data fast. There was a line on > > the > >>>CPU, used as a bus request. The DMA module requested control of the > > BUS, > >>>and while the CPU granted access, the CPU just stayed idle. >>> >>>Now, with PCI, any devices on the PCI bus can initiate requests > > (provided > >>>they have master capability). The request from one device to another > > are > >>>theorically transparent to other devices on the bus. So, any board > > could > >>>access memory, while the CPU is concurently processing. Of course, you >>>can't have two transactions at the same time on the bus, but the idea is >>>that, appart from initial configuration, the devices desn't have to rely > > on > >>>other devices on the bus. >>> >>>PCI masters can perform burst transfers. PCI target can reply to burst >>>read/write requests. A target doesn't have to comply to the burst > > request, > >>>if it doesn't support it, or can initiate aborts after transfering part > > of > >>>the burst. The master can then re-start from where the target have > > aborted. > >>>The thing to remember is that targets can not initiate requests on their > > own > >>>over the PCI bus. So, if you wish to access memory, you need to have a >>>master. And if you do have a master, and you know where the memory is > > (ex, > >>>memory location configured by the software or driver in CPU), then your >>>device can access the memory on it's own, without having to wait for >>>specific request from the main CPU. PCI video cards that used what's > > called > >>>in the industry as 'shared memory' use this principle. Though, this of >>>course may slow down other devices on the bus, but still look > > transparent to > >>>them. >>> >>> >>>>From: sayedzeeshan@gmail.com >>>>Reply-To: "Discussion list about free,open source PCI IP core" >>>>pci@opencores.org> >>>>To: pci@opencores.org >>>>Subject: [pci] PCI DMA >>>>Date: Mon, 13 Dec 2004 08:28:21 +0100 >>> >>> >>>>Hi >>>>1. My question is that Can PCI target do DMA transfers... or is it >>>>confined only to PCI master.... >>>>2. If there is a burst mode support in target, is there any need to do >>>>DMA transfers? >>>>_______________________________________________ >>>>http://www.opencores.org/mailman/listinfo/pci >>> >>>_______________________________________________ >>>http://www.opencores.org/mailman/listinfo/pci >>> >> >> >>-- >>Sayed Zeeshan Asghar >>_______________________________________________ >>http://www.opencores.org/mailman/listinfo/pci >> > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/pci > -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

(slaves).


burst transfer - consists of a single address phase followed by two or more
data phases (data on each clock-the highest transfer speed on PCI bus).

[Address and Command][Dtat][Data][Data]...[Data]

single transfer - consists of a single address phase followed by single
data phase (very slow in comparison to burst transfer).

[Address and Command][Data][Address and Command][Data]...[Address and
Command][Data]

We attempt to send/receive block of data to/from PCI card
capable of burst transfer. Motherboard chip set will transfer
each data object (up to 32-bits in 32-bit implementation) as single
transfer.

Our PCI card is capable of burst transfer or not, we have only sereies of
single transfers.

We can get motherboard chip set to respond with burst transfer
if we use PCI bus master card.

I am trying to use simple language to explain what happens.
Regards,
Richard

Thank you all for your responses.
I know The "target-only" is not very common these days, but we have to
use that for specific reasons. How will you tell the arbitrer about
the transaction....B/w Master DRAM and our "target-only" device.
--
Sayed Zeeshan Asghar

If your board is target-only, it can not initiate transfer. So, this meen
that it need some other board on the PCI bus (either on the same bus, or
over a PCI bridge), to initiate a burst transfer.

Memory itself is accessed via a memory controler. If the memory controler
have direct transfer capability (which I doubt), then it could transfer data
in burst. But usually, the memory controler is a target-only. So, unless
the memory controler have DMA capability over the PCI bus, than you can't
transfer data unless initiated by a third device on the bus (ex: CPU).

In a typical modern PC, you have the processor (CPU) having address lines.
It access any address without much care if it's memory, memory mapped IO,
system peripherial, ... The CPU connect directly to the 'north-bridge'
chip. That north-bridge chip is an ASIC containing a few controlers, like
the memory controler, the AGP controler and the PCI bus controler. Some
also have a direct hyperlink access to the south-bridge. The south-bridge
having other controlers, like ISA bus (on older systems), and other
low-order controlers.

When the CPU ask for data at a memory location, the north-bridge is
configured to know where to send or request the data. However, It doesn't
actually initiate the request on it's own, it just respond to the CPU.
However, he may be told to do burst transfer, on request of the CPU. This
would have to be verified with the system drivers, and the capability of the
north-bridge.