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Configuration Space Read in burst mode
by Unknown on Dec 15, 2004 |
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Hello @ all.
I'm working on designing a pci-master with an fpga. Here's my question: Is it possible to read out a device's Configuration Space (with command Ah on CBE) in burst mode, e.g. presenting the address 0h once and then have the target delivered the whole CS header resp. Space? I didn't find a explicit no anywhere in literature. On the timing diagrams i saw there was always FRAME# deasserted after the first address phase, indicating a non-burst mode. CS readout works fine in non-burst mode with the fpga. Thanks for Your answers. Chris |
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Configuration Space Read in burst mode
by Unknown on Dec 15, 2004 |
Not available! | ||
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Accesing a Configuration space in burst mode is not allowed in PCI
specification
Regards
Wojciech Cynk
----- Original Message -----
From: xxxkryzxxx@web.de>
To: pci@opencores.org>
Sent: Wednesday, December 15, 2004 1:46 PM
Subject: [pci] Configuration Space Read in burst mode
Hello @ all.
I'm working on designing a pci-master with an fpga. Here's my question: Is it possible to read out a device's Configuration Space (with command Ah on CBE) in burst mode, e.g. presenting the address 0h once and then have the target delivered the whole CS header resp. Space? I didn't find a explicit no anywhere in literature. On the timing diagrams i
saw there was always FRAME# deasserted after the first address phase,
indicating a non-burst mode.
CS readout works fine in non-burst mode with the fpga.
Thanks for Your answers. Chris
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
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Configuration Space Read in burst mode
by Unknown on Dec 16, 2004 |
Not available! | ||
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You will find some information about Configuration Access in burst mode
in the PCI Local Bus Spec (2.3), 3.2.2.3.4. Selection of a Device's Configuration Space: "... The configuration commands, like other commands, allow data to be accessed using ... multiple data phases in a burst. The target ... is not required to handle a configuration transaction that consists of multiple data phases. ..." Due to the nature of generating config cycles in PC-AT based systems(CF8/CFC), you will unlikely find config bursts initiated by the CPU in such systems. Hope that helps. Gerd Ternathe
-----Original Message-----
From: pci-bounces@opencores.org
[mailto:pci-bounces@opencores.org] On Behalf Of xxxkryzxxx@web.de
Sent: Wednesday, December 15, 2004 1:46 PM
To: pci@opencores.org
Subject: [pci] Configuration Space Read in burst mode
Hello @ all.
I'm working on designing a pci-master with an fpga. Here's my question:
Is it possible to read out a device's Configuration Space
(with command Ah on CBE) in burst mode, e.g. presenting the
address 0h once and then have the target delivered the whole
CS header resp. Space?
I didn't find a explicit no anywhere in literature. On the
timing diagrams i saw there was always FRAME# deasserted after
the first address phase, indicating a non-burst mode.
CS readout works fine in non-burst mode with the fpga.
Thanks for Your answers. Chris
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
|
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