Send Pci mailing list submissions to pci@opencores.org To subscribe or unsubscribe via the World Wide Web, visit http://www.opencores.org/mailman/listinfo/pci or, via email, send a message with subject or body 'help' to pci-request@opencores.org You can reach the person managing the list at pci-owner@opencores.org When replying, please edit your Subject line so it is more specific than "Re: Contents of Pci digest..." Today's Topics: 1. RE: PCI DMA (delta trinity) 2. Re: PCI DMA (Sayed Zeeshan) 3. Re: PCI DMA (Richard Sliwinski) 4. Re: PCI DMA (Stephen Williams) 5. Re: PCI DMA (Richard Sliwinski) 6. Re: PCI DMA (Sayed Zeeshan) 7. Configuration Space Read in burst mode (xxxkryzxxx@web.de) 8. Re: Configuration Space Read in burst mode (Wojciech Cynk ARCO) ---------------------------------------------------------------------- Message: 1 Date: Mon, 13 Dec 2004 17:56:24 -0500 From: "delta trinity" deltatrinity@hotmail.com> Subject: RE: [pci] PCI DMA To: pci@opencores.org Message-ID: BAY101-F57F8443FEC831D3E4883ED2AB0@phx.gbl> Content-Type: text/plain; format=flowed Targets can not initiate transfers. Only masters can. DMA was mainly used in the old days of ISA/EISA bus where the CPU was the master, and all devices were slaves. On those legacy bus, there were no way for the processor to transfer multiple data fast. There was a line on the CPU, used as a bus request. The DMA module requested control of the BUS, and while the CPU granted access, the CPU just stayed idle. Now, with PCI, any devices on the PCI bus can initiate requests (provided they have master capability). The request from one device to another are theorically transparent to other devices on the bus. So, any board could access memory, while the CPU is concurently processing. Of course, you can't have two transactions at the same time on the bus, but the idea is that, appart from initial configuration, the devices desn't have to rely on other devices on the bus. PCI masters can perform burst transfers. PCI target can reply to burst read/write requests. A target doesn't have to comply to the burst request, if it doesn't support it, or can initiate aborts after transfering part of the burst. The master can then re-start from where the target have aborted. The thing to remember is that targets can not initiate requests on their own over the PCI bus. So, if you wish to access memory, you need to have a master. And if you do have a master, and you know where the memory is (ex, memory location configured by the software or driver in CPU), then your device can access the memory on it's own, without having to wait for specific request from the main CPU. PCI video cards that used what's called in the industry as 'shared memory' use this principle. Though, this of course may slow down other devices on the bus, but still look transparent to them. ------------------------------ Message: 2 Date: Tue, 14 Dec 2004 10:06:16 +0500 From: Sayed Zeeshan sayedzeeshan@gmail.com> Subject: Re: [pci] PCI DMA To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Message-ID: 7973b14304121321064352377@mail.gmail.com> Content-Type: text/plain; charset=US-ASCII Thank you very much delta trinity for reply. But the problem is that our target supports burst transfers, so how would one tranfser data to RAM directly in burst mode??? Is it the task of cpu or what? On Mon, 13 Dec 2004 17:56:24 -0500, delta trinity deltatrinity@hotmail.com> wrote: -- Sayed Zeeshan Asghar ------------------------------ Message: 3 Date: Tue, 14 Dec 2004 09:00:15 -0500 From: "Richard Sliwinski" rvs@interlog.com> Subject: Re: [pci] PCI DMA To: "Sayed Zeeshan" sayedzeeshan@gmail.com>, "Discussion list about free, open source PCI IP core" pci@opencores.org> Message-ID: 9ea91dd1@richards> Content-Type: text/plain; charset="iso-8859-1" Motherboard chip sets do not support burst transfer to PCI targets (slaves). ****************************************************************** If you need burst transfer you have to implement PCI master. I hope someone can prove me wrong. Regards, Richard ----- Original Message ----- From: "Sayed Zeeshan" sayedzeeshan@gmail.com> To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Sent: Tuesday, December 14, 2004 12:06 AM Subject: Re: [pci] PCI DMA ------------------------------ Message: 4 Date: Tue, 14 Dec 2004 09:45:05 -0800 From: Stephen Williams steve@icarus.com> Subject: Re: [pci] PCI DMA To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Message-ID: 41BF26A1.1090601@icarus.com> Content-Type: text/plain; charset=us-ascii; format=flowed Richard Sliwinski wrote: Anybody working on PCI devices or device drivers must have a good sense for all this. Without a working understanding, you are doomed to a confused failure. I hear good things about books published by MindShare Inc. http://www.mindshare.com/>. A PCI device can accept a burst as a target, or can initiate a burst as a master. Any device in a typical PCI bus can be a master at any given moment, it is up to the arbiter (part of the motherboard) to grant a device access to the bus. So when one says that a device is a "target", then one is saying that a device is a target of a "transaction" and there is another master accessing that target device. Every PCI device supports at least being a target. When one says a device is "target-only" then one is saying that the device is not able to initiate a transaction. Target-only devices are relatively uncommon these days. One might think of a video card, for example, as a target-only device (although even that is probably not always true.) It is most common for a PCI device (i.e. ethernet card) to be capable of bus mastering. Without that capability, there is no DMA to that card. For example, an ethernet card is the target of transactions when the host writes registers to configure a transfer of a block of data to the wire. Then when started it initiates reads from memory to get the data. I.e. it acts as a master. It directly accesses the memory buffer for itself. It does "DMA". So a "target-only" device cannot do DMA. Burst mode has nothing to do with it. If a device does burst reads (i.e. the *device* reads from the PCI) then it can do DMA, and how you set it up is described in the device documentation. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." ------------------------------ Message: 5 Date: Tue, 14 Dec 2004 15:11:28 -0500 From: "Richard Sliwinski" rvs@interlog.com> Subject: Re: [pci] PCI DMA To: "Discussion list about free,open source PCI IP core" pci@opencores.org> Message-ID: df5e1dd1@richards> Content-Type: text/plain; charset="iso-8859-1"
(slaves).


burst transfer - consists of a single address phase followed by two or more
data phases (data on each clock-the highest transfer speed on PCI bus).

[Address and Command][Dtat][Data][Data]...[Data]

single transfer - consists of a single address phase followed by single
data phase (very slow in comparison to burst transfer).

[Address and Command][Data][Address and Command][Data]...[Address and
Command][Data]

We attempt to send/receive block of data to/from PCI card
capable of burst transfer. Motherboard chip set will transfer
each data object (up to 32-bits in 32-bit implementation) as single
transfer.

Our PCI card is capable of burst transfer or not, we have only sereies of
single transfers.

We can get motherboard chip set to respond with burst transfer
if we use PCI bus master card.

I am trying to use simple language to explain what happens.
Regards,
Richard

------------------------------ Message: 6 Date: Wed, 15 Dec 2004 10:12:03 +0500 From: Sayed Zeeshan sayedzeeshan@gmail.com> Subject: Re: [pci] PCI DMA To: "Discussion list about free, open source PCI IP core" pci@opencores.org> Message-ID: 7973b14304121421122c0001c8@mail.gmail.com> Content-Type: text/plain; charset=US-ASCII Thank you all for your responses. I know The "target-only" is not very common these days, but we have to use that for specific reasons. How will you tell the arbitrer about the transaction....B/w Master DRAM and our "target-only" device. -- Sayed Zeeshan Asghar ------------------------------ Message: 7 Date: Wed, 15 Dec 2004 13:46:16 +0100 From: xxxkryzxxx@web.de Subject: [pci] Configuration Space Read in burst mode To: pci@opencores.org Message-ID: 200412151246.iBFCkGdO006735@www.opencores.org> Hello @ all. I'm working on designing a pci-master with an fpga. Here's my question: Is it possible to read out a device's Configuration Space (with command Ah on CBE) in burst mode, e.g. presenting the address 0h once and then have the target delivered the whole CS header resp. Space? I didn't find a explicit no anywhere in literature. On the timing diagrams i saw there was always FRAME# deasserted after the first address phase, indicating a non-burst mode. CS readout works fine in non-burst mode with the fpga. Thanks for Your answers. Chris ------------------------------ Message: 8 Date: Wed, 15 Dec 2004 14:27:13 +0100 From: "Wojciech Cynk ARCO" wojtek@arco.pl> Subject: Re: [pci] Configuration Space Read in burst mode To: "Discussion list about free,open source PCI IP core" pci@opencores.org> Message-ID: 1308a8c0@marcin> Content-Type: text/plain; charset="iso-8859-2" Accesing a Configuration space in burst mode is not allowed in PCI specification Regards Wojciech Cynk ----- Original Message ----- From: xxxkryzxxx@web.de> To: pci@opencores.org> Sent: Wednesday, December 15, 2004 1:46 PM Subject: [pci] Configuration Space Read in burst mode
i
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