Hello and thank you for reading my post ! I would like to implement the PCI core bridge in a spartan III fpga, but I have problems when synthesizing the rtl code with ise 6.3. When compiling 'pci_wb_slave_unit', I have a "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13". I just would have the pci bridge (pciwishbone interface), not the CRT stuff. Has anyone already succeed it ? Could someone give me his whole directory ? Thanks in advance ! Sam _________________________________________________________________ MSN vous envoie des nouvelles toutes fraîches par SMS où que vous vous trouviez! http://www.fr.msn.ch/mobile/