I added extra capacitors in order to improve the power rails by the Cyclone EP1C12Q240C8 FPGA. Now on the scope the 1.5V and 3.3V looks very clean. However I still get the SERR errors. This is dispite the Quartus reporting that it can meet timing for 33Mhz PCI. I am being forced to consider buying a commercial core. One thing I have discovered is that they are all qualified for specific pin outs, it seems they only guarentee they work if you use these. I suggest that anyone looking to do PCI lifts the pin out from Altera. What I noticed that they don't use every I/O in a bank (with the pin out for the 240QFP 5 were spare), unused I/O's are grounded. Maybe they have to do something like that to make it work. Dave Warren dave@luscher.co.uk

I've been told my an altera FAE that 4 grounded i/o pins are equivalent to a real ground. Also there are limitations to how many pins you should use in a bank and those limitationas are detailed in the data sheet. A few possibles to check out first before you buy a core: - It sounds like your clock could be messed up. Look for excessive jitter on the clock line, and also look for any hitches in the rising and falling edges around the Vih and Vil levels. - Review the routing of your clock line. Make sure it is a straight shot, with a minimum # of vias and branches. Try to match the impedance of the line with a series resistor. Too low a resistor will give you overshoot, to high a resistor or branches and vias in the wrong locations could give hitches. - Review the routing of the data path. Verify that al lines are reasonably routed and roughly the same length long. -----Original Message----- From: Dave Warren [mailto:dave@luscher.co.uk] Sent: Friday, January 21, 2005 9:10 AM To: pci@opencores.org Subject: [pci] Opencore PCI in Altera Cyclone - SERR update I added extra capacitors in order to improve the power rails by the Cyclone EP1C12Q240C8 FPGA. Now on the scope the 1.5V and 3.3V looks very clean. However I still get the SERR errors. This is dispite the Quartus reporting that it can meet timing for 33Mhz PCI. I am being forced to consider buying a commercial core. One thing I have discovered is that they are all qualified for specific pin outs, it seems they only guarentee they work if you use these. I suggest that anyone looking to do PCI lifts the pin out from Altera. What I noticed that they don't use every I/O in a bank (with the pin out for the 240QFP 5 were spare), unused I/O's are grounded. Maybe they have to do something like that to make it work. Dave Warren dave@luscher.co.uk _______________________________________________ http://www.opencores.org/mailman/listinfo/pci

Unused I/O's connected to ground are "programmable GND".
They're used to reduce Simultaneous Switching Noise.
Look at Altera AN315 for more information.

Stephane Debieux

Hi Dave,

I'm successfully using an EP1C12Q240C7 with the Opencores
PCI bridge. There were some problems ... but these were
all related to my wishbone-to-avalon bridge implementation.

> What I noticed that they don't use every I/O in a bank

Yep ... this is important to make timing.

I'm not sure what you cooked up on the wishbone target
side, but if your trying to access SDRAM and using the
Altera controller ... good luck ... the controller's
performance is awful -- lots of timeouts. Once I switched
to on-chip RAM life was good ;-)


Regards,
--Scott

Hi Scott,

Nice to hear that you have EP1C12Q240C7 working. Is this 33Mhz ?

I needed almost all the I/O's otherwise my application won't work. What I am
doing is replacing a PCI bridge chip and FPGA on an existing embedded
controller with a larger capicity FPGA including the PCI core. On the
wishbone side I have a 32 bit wide FIFO. I just use the Opencores PCI as a
target, my controller has DMA and can burst write very long bursts on data
out to the PCI. I also have some external static RAM which I use as a big
buffer.

I used the pin out just to make the PCB layout easy, I ensured the PCI clock
went to a dedicated input. I chose the 240QFP because it was easier to work
with than BGA.

I would be interested in the constraints you gave to Quartus if you could
e-mail them direct. How did you decide how meny I/O's it was safe to use?

Regards

Dave

Hi Daniel Thanks for the good suggestions. ----- Original Message ----- From: "DANIEL BYRNE" daniel.byrne@adtran.com> To: "'Discussion list about free, open source PCI IP core'" pci@opencores.org> Sent: Friday, January 21, 2005 3:41 PM Subject: RE: [pci] Opencore PCI in Altera Cyclone - SERR update
a real ground. Also there are limitations to how many pins you should use
in a bank and those limitationas are detailed in the data sheet.

Any idea which chapter of the data sheet has the limitations?


on the clock line, and also look for any hitches in the rising and falling
edges around the Vih and Vil levels.

I use a quartz crystal clock source and a clock distribution chip, each
33Mhz load has it's own line and they are carefully matched lenghts. The two
loads are the Cyclone chip and my embedded controller Intel GC80303. On the
FPGA the clock line did have a large amount of over/under shoot. I tried to
clean it up with a 50R to the 1.5V which is Cyclone core voltage. It
certainly looked cleaner, however it did not fix the problem.


with a minimum # of vias and branches. Try to match the impedance of the
line with a series resistor. Too low a resistor will give you overshoot, to
high a resistor or branches and vias in the wrong locations could give
hitches.

The routing is point to point and I avoid 90 bends.


reasonably routed and roughly the same length long.

This is a tough one, in order the get enough I/O's that are PCI compatable I
have to use opposit sides of the chip, so 8 AD lines are about 2" longer
than the rest.


Cyclone

that

Hi Dave!

Dave Warren escribió:

Haven't you grounded unused I/ O's? Try setting every unused I/O as input and ground them. Good Luck! -- Técnico Andrés Trapanotto INSTITUTO NACIONAL DE TECNOLOGÍA INDUSTRIAL Centro de Investigación Telecomunicaciones, Electrónica e Informática Teléfono (54 11) 4724 6300 Interno 6362 andres_t@inti.gov.ar ___________________________________________ 0800 444 4004 | www.inti.gov.ar

Page 59 of AN-315 talks about "programmable ground". I believe this is just talking about what your unused, unconnected IO pins are set to. In high speed design you should never leave them tri-stated. So make sure all unused, unconnected IO are set to outputs, driving GND. You mentioned the PCI interface, the requirements are: Max length for 32-bit interface signals = 1.5" Max length for additional 64-bit interface signals = 2.0" PCI CLK length = 2.5" +/- 0.1". Note that the PCI CLK length is a specific value, and not a maximum. ----- Original Message ----- From: Andrés Trapanottoandres_t@i...> To: Date: Fri Jan 21 18:25:18 CET 2005 Subject: [pci] Opencore PCI in Altera Cyclone - SERR update

Just a few more thoughts. I'm going to be doing the same thing you are, replacing a PLX-9080 PCI bridge by using a PCI core in an Altera part. If I understand things, you're getting SERR's, but can't narrow things down to the exact cause. 1) If the problem is with your board, I wouldn't expect someone else's core to be a solution. If you did use another core and it happened to work, I would be very wary of long term reliability. 2) Have you looked deeper in the logic to see the exact cause of the SERR? Just to make sure it's not a bug with the PCI core or your glue interface logic. 3) Have you tried using the SERR occurance as a trigger to a scope or logic analyzer? Once you get this, then it's easier to probe clocks and signals to see if there's some type of disturbance near the trigger point. 4) Even if you can't get a good trigger on the error, looking at the PCI signals and your custom IO signals may show some type of disturbance. Also, are there any possible external sources of noise (motors, for example, but I don't know your exact app)? 5) Is it possible to try it with your clocks slowed down (including the PCI clock)? 6) An obvious one, but make sure that the logic is using the PCI clock to clock the appropriate part of the core. Also, is it possible switch around your clocking, like use the PCI clock for everything, just to see if there is a problem with a certain clock (obviously you must use the PCI clk to clock the PCI portion of the core)? 7) When you say Quartus says it can meet 33MHz timing, is this just the clock freq? Perhaps you're not meeting setup/hold/tco times on PCI or your custom IO. I'm not familiar enough with the PCI core, so I can't claim any expertise on it, but maybe one of my suggestions will help. ----- Original Message ----- From: Dave Warrendave@l...> To: Date: Fri Jan 21 16:10:23 CET 2005 Subject: [pci] Opencore PCI in Altera Cyclone - SERR update