Hi! I'm working on a project in school based on OpenCores PCI core and have some problems getting it to work. I have taken all the needed files from the pci/rtl directory and modified the top.v file from the crt application to include our project written in VHDL. So far all seems to be working. But when I add input signals to my VHDL application they all exist in the RTL view but when I synthesize the code I can no longer see the inputs and it's not possible to add them to the ucf file. Defining outputs are no problems and all show up in the ucf file. I don't know Verilog but to me all seems good and I have added the inputs the way the PCI inputs are defined. Has anyone experienced this? Help would be greatly appreciated! I'm using a Memec Spartan 2 PCI board, Synplify Pro 8.0 and Xilinx WebPack 6.3. Thanks in advance! /Mikael Pettersson _________________________________________________________________ Auktioner: Tjäna en hacka på gamla prylar http://tradera.msn.se

I respond to my own message because I was able to solve the problem. The problem was that I needed to define the inputs in a different way. Well I have learnt some more Verilog... ----- Original Message ----- From: Mikael Petterssonmipson@h...> To: Date: Mon Feb 14 12:18:39 CET 2005 Subject: [pci] Problems adding input signals