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Synthesis Trouble
by Unknown on Mar 6, 2005 		Not available!
Hello everyone, Thanks in advance for any help, and sorry for this horribly long email. I have spent the last few months modifying the PCI Bridge module to remove the wishbone bus and replace it with a "generic" bus, easily convertible to IPIF. To do this, i didn't touch the PCI master module, configuration space and FIFOS. I changed the pci_wb_slave.v module drastically, though. The changes there left the code structure entirely the same (the FSM is the same, only with a few different assignment in every case) which also goes for the rest of the file. On the higher level modules, i changed the wiring accordingly. The next step is synthesis, which gives me big trouble. I am using Xilinx ISE to generate a simulation model, and modelsim 6.0 to run it. I am new to the synthesis procedure and thus i am stuck without knowing what to do. I would be most grateful for any suggestions. The pci_wb_slave.v module, as it is, has the same coding style as before. I always specify a value for a register inside an if and in the corresponding else. As for the always@ block of the FSM, i set a "default" value for every register and then change it accordingly depending on the state and the inputs. I get no FF/Latch warnings. I have checked the timing constraints i entered (30 ns for the PCI - 33Mhz and 10 nz for the generic bus) and they are both met. However, i do get some messages i would like some help on to determine if they are worrying or not: 1). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. As i have accepted the configuration space as a black box, and because the severity is "INFO", not "WARNING", i didn't really pay attention to this message. Is there any chance this decision by the synthesizer would be the incorrect one? 2). WARNING:Xst:1467 - pci_wb_slave.v line 462: Reset or set value is not constant in . It could involve simulation mismatches This is a bit weird since this warning shows itself for each assignment of the first if body of: (i changed the always@ block this way to make it synthesizable) always@(posedge reset_in or posedge wb_clock_in or posedge decode_en) begin if (reset_in) begin img_wallow of the block are unconnected in block . I've looked into pci_conf_space.v and the outputs of the said module *are* used (in a boolean expression). I've also looked at the synthesis report of the pci_conf_space module, and while it mentions some signals that are not used and therefore removed, the outputs of the said module are not mentioned. I don't know what kind of trimming the synthesizer performs, but is there anything going on? Apart from those i get some signals that are not used, but everything else is fine. When trying to simulate the generated simulation model, i get three types of error messages: (Xilinx and FPGA constants are defines, so RAMB4_S16_S16 is being used for memory) 1). # *** monitor - PCI External RESET_L invalid 'hx, at 2000 # ** Error: D:/Xilinx/verilog/src/simprims/X_RAMB16_S36_S36.v(1621): $hold( posedge CLKB:7341 ps, negedge ADDRB[4] &&& ENB:7367 ps, 219 ps ); # Time: 7367 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_fifos_wbr_fifo_storage_Mram_mem_inst_ramb_1 # ** Error: D:/Xilinx/verilog/src/simprims/X_RAMB16_S36_S36.v(1617): $hold( posedge CLKB:7341 ps, negedge ADDRB[2] &&& ENB:7444 ps, 219 ps ); # Time: 7444 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_fifos_wbr_fifo_storage_Mram_mem_inst_ramb_1 # *** monitor - PCI GNT_L unknown 'hxx, at 15000 The violation occurs at a memory cell, from the raddr_out output of the pci_wbw_fifo_control module. This output is driven by a mux. I would suppose the simulation model of this latch (and the rest of the ciruit) had enough delay. 2). # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(42): $recovery( negedge RST:9037072 ps, posedge CLK &&& (rst_clk_enable == 1):9037212 ps, 600 ps ); # Time: 9037212 ps Iteration: 1 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_addr_hit_old_3398 # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(42): $recovery( negedge RST:9037072 ps, posedge CLK &&& (rst_clk_enable == 1):9037212 ps, 600 ps ); # Time: 9037212 ps Iteration: 1 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_addr_hit_3418 I don't quite know that this means. 3). # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(46): $width( posedge RST:10980614 ps, :10981327 ps, 738 ps ); # Time: 10981327 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_img_wallow_3435 # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(46): $width( posedge RST:10980614 ps, :10981327 ps, 738 ps ); # Time: 10981327 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_img_wallow_old_3697 # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(47): $width( posedge SET:12259784 ps, :12260350 ps, 738 ps ); # Time: 12260350 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_completion_allow_old_3139 # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(47): $width( posedge SET:12259784 ps, :12260350 ps, 738 ps ); # Time: 12260350 ps Iteration: 0 Instance: /SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_completion_allow_3516 Same here. I am very grateful for any suggestions. This is the first time i'm trying to synthesize something, and the PCI Bridge is a bit too big :-) Thank you in advance for any help to get me moving on, and sorry for this horribly long email. Mihelogiannakis Giorgos
Synthesis Trouble
by Unknown on Mar 7, 2005 		Not available!
Hi Giorgos, Please find attached the test_synth module I have created form your always block. The way I have done it, it synthesizes with no warnings. Usually, whenever you define synchronous logic, beside clock and reset, there is no need for other signals in the sensitivity list. Also, in my designs, I always simulate RTL first, for functionality. It is way faster. I will simulate post place&route only if I have problems in the lab that I cannot debug otherwise. No such simulations so far ... I have removed the delay statements in the synchronous logic, since it will generate false warnings in synthesis. I had HUGE issues with the ISE synthesis tools. I always use Synplify for synthesis: much, much better. Hope this helps, Ovidiu --------------------------------------- Resource Usage Report for test_synth Mapping to part: xc2v40cs144-6 Cell usage: FDC 18 uses I/O primitives: 30 IBUF 12 uses OBUF 18 uses BUFGP 1 use I/O Register bits: 0 Register bits not including I/Os: 18 (3%) Global Clock Buffers: 1 of 16 (6%) Mapping Summary: Total LUTs: 18 (3%) Mapper successful! Process took 0h:0m:3s realtime, 0h:0m:3s cputime ###########################################################] ----- Original Message ----- From: "Mihelogiannakis giorgos" mihelog@csd.uoc.gr> To: pci@opencores.org> Sent: Sunday, March 06, 2005 1:51 PM Subject: [pci] Synthesis Trouble
Hello everyone,

Thanks in advance for any help, and sorry for this horribly long

email.

I have spent the last few months modifying the PCI Bridge module

to
remove the wishbone bus and replace it with a "generic" bus, easily convertible to IPIF. To do this, i didn't touch the PCI master module, configuration space and FIFOS. I changed the pci_wb_slave.v module drastically, though. The changes there left the code structure entirely the same (the FSM is the same, only with a few different assignment in every case) which also goes for the rest of the file. On the higher level modules, i changed the wiring accordingly. The next step is synthesis, which gives me big trouble. I am using Xilinx ISE to generate a simulation model, and modelsim 6.0 to run it. I am new to the synthesis procedure and thus i am stuck without knowing what to do. I would be most grateful for any suggestions. The pci_wb_slave.v module, as it is, has the same coding style as before. I always specify a value for a register inside an if and in the corresponding else. As for the always@ block of the FSM, i set a "default" value for every register and then change it accordingly depending on the state and the inputs. I get no FF/Latch warnings. I have checked the timing constraints i entered (30 ns for the PCI - 33Mhz and 10 nz for the generic bus) and they are both met. However, i do get some messages i would like some help on to determine if they are worrying or not: 1). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. As i have accepted the configuration space as a black box, and because the severity is "INFO", not "WARNING", i didn't really pay attention to this message. Is there any chance this decision by the synthesizer would be the incorrect one? 2). WARNING:Xst:1467 - pci_wb_slave.v line 462: Reset or set value is not constant in . It could involve simulation mismatches This is a bit weird since this warning shows itself for each assignment of the first if body of: (i changed the always@ block this way to make it synthesizable) always@(posedge reset_in or posedge wb_clock_in or posedge decode_en) begin if (reset_in) begin img_wallow of the block are unconnected in block . I've looked into pci_conf_space.v and the outputs of the said module *are* used (in a boolean expression). I've also looked at the synthesis report of the pci_conf_space module, and while it mentions some signals that are not used and therefore removed, the outputs of the said module are not mentioned. I don't know what kind of trimming the synthesizer performs, but is there anything going on? Apart from those i get some signals that are not used, but everything else is fine. When trying to simulate the generated simulation model, i get three types of error messages: (Xilinx and FPGA constants are defines, so RAMB4_S16_S16 is being used for memory) 1). # *** monitor - PCI External RESET_L invalid 'hx, at 2000 # ** Error: D:/Xilinx/verilog/src/simprims/X_RAMB16_S36_S36.v(1621): $hold( posedge CLKB:7341 ps, negedge ADDRB[4] &&& ENB:7367 ps, 219 ps ); # Time: 7367 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_fifos_wbr_fifo_storage_Mram_
mem_inst_ramb_1
# ** Error: D:/Xilinx/verilog/src/simprims/X_RAMB16_S36_S36.v(1617):
$hold( posedge CLKB:7341 ps, negedge ADDRB[2] &&& ENB:7444 ps, 219 ps );
# Time: 7444 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_fifos_wbr_fifo_storage_Mram_
mem_inst_ramb_1
# *** monitor - PCI GNT_L unknown 'hxx, at 15000

The violation occurs at a memory cell, from the raddr_out output of the
pci_wbw_fifo_control module. This output is driven by a mux. I would
suppose the simulation model of this latch (and the rest of the ciruit)
had enough delay.

2). # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(42): $recovery(
negedge RST:9037072 ps, posedge CLK &&& (rst_clk_enable == 1):9037212 ps,
600 ps );
# Time: 9037212 ps Iteration: 1 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_addr_hit_
old_3398
# ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(42): $recovery( negedge
RST:9037072 ps, posedge CLK &&& (rst_clk_enable == 1):9037212 ps, 600 ps
);
# Time: 9037212 ps Iteration: 1 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_addr_hit_
3418

I don't quite know that this means.

3). # ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(46): $width( posedge
RST:10980614 ps, :10981327 ps, 738 ps );
# Time: 10981327 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_img_wallow_34
35
# ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(46): $width( posedge
RST:10980614 ps, :10981327 ps, 738 ps );
# Time: 10981327 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_img_wallow_ol
d_3697
# ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(47): $width( posedge
SET:12259784 ps, :12260350 ps, 738 ps );
# Time: 12260350 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_completio
n_allow_old_3139
# ** Error: D:/Xilinx/verilog/src/simprims/X_FF.v(47): $width( posedge
SET:12259784 ps, :12260350 ps, 738 ps );
# Time: 12260350 ps Iteration: 0 Instance:

/SYSTEM/bridge32_top/bridge_wishbone_slave_unit_wishbone_slave_del_completio
n_allow_3516
Same here. I am very grateful for any suggestions. This is the first time i'm trying to synthesize something, and the PCI Bridge is a bit too big :-) Thank you in advance for any help to get me moving on, and sorry for this horribly long email. Mihelogiannakis Giorgos _______________________________________________ http://www.opencores.org/mailman/listinfo/pci
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